基于人工神经网络的芯片级信号完整性分析与串扰预测

A. Ilumoka
{"title":"基于人工神经网络的芯片级信号完整性分析与串扰预测","authors":"A. Ilumoka","doi":"10.1109/ISQED.2002.996725","DOIUrl":null,"url":null,"abstract":"Recent ITRS predictions indicate that by the year 2011, the billion transistor monolithic die will be a reality. This clearly poses a challenge to gigascale integrated circuit design with regard to provision of multilevel interconnect wiring for the distribution of power, data and control signals to all parts of a chip. This paper addresses the problem of characterization, modeling and verification of 3D chip level interconnect crosstalk. The novel methodology proposed involves topological decomposition of interconnects into standard cells and the creation of parameterized models of these primitive structures using neural networks. Experimental results from a high performance operational amplifier demonstrates the viability of the approach.","PeriodicalId":20510,"journal":{"name":"Proceedings International Symposium on Quality Electronic Design","volume":null,"pages":null},"PeriodicalIF":0.0000,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"Chip level signal integrity analysis and crosstalk prediction using artificial neural nets\",\"authors\":\"A. Ilumoka\",\"doi\":\"10.1109/ISQED.2002.996725\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Recent ITRS predictions indicate that by the year 2011, the billion transistor monolithic die will be a reality. This clearly poses a challenge to gigascale integrated circuit design with regard to provision of multilevel interconnect wiring for the distribution of power, data and control signals to all parts of a chip. This paper addresses the problem of characterization, modeling and verification of 3D chip level interconnect crosstalk. The novel methodology proposed involves topological decomposition of interconnects into standard cells and the creation of parameterized models of these primitive structures using neural networks. Experimental results from a high performance operational amplifier demonstrates the viability of the approach.\",\"PeriodicalId\":20510,\"journal\":{\"name\":\"Proceedings International Symposium on Quality Electronic Design\",\"volume\":null,\"pages\":null},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2002-08-07\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Proceedings International Symposium on Quality Electronic Design\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ISQED.2002.996725\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings International Symposium on Quality Electronic Design","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ISQED.2002.996725","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 0

摘要

最近的ITRS预测表明,到2011年,十亿晶体管单片芯片将成为现实。这显然对千兆级集成电路设计提出了挑战,因为它需要提供多级互连布线,以便将电源、数据和控制信号分配到芯片的所有部分。本文研究了三维芯片级互连串扰的表征、建模和验证问题。提出的新方法包括将互连拓扑分解为标准单元,并使用神经网络创建这些原始结构的参数化模型。一个高性能运算放大器的实验结果证明了该方法的可行性。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
Chip level signal integrity analysis and crosstalk prediction using artificial neural nets
Recent ITRS predictions indicate that by the year 2011, the billion transistor monolithic die will be a reality. This clearly poses a challenge to gigascale integrated circuit design with regard to provision of multilevel interconnect wiring for the distribution of power, data and control signals to all parts of a chip. This paper addresses the problem of characterization, modeling and verification of 3D chip level interconnect crosstalk. The novel methodology proposed involves topological decomposition of interconnects into standard cells and the creation of parameterized models of these primitive structures using neural networks. Experimental results from a high performance operational amplifier demonstrates the viability of the approach.
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