基于概率电感的精确芯片延迟预测模型

Z. Shirmohammadi, Masoumeh Taali, H. Sabzi
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引用次数: 3

摘要

多核和多核系统的可靠性取决于核间通信结构的正确功能。然而,在这些片上通信中,核心之间的数据传输会严重面临串扰故障。时间延迟是串扰故障的最大影响因素,因此提供一个预测延迟的模型可以减少设计人员提供更有效的机制来减少串扰故障的时间。为此,本文提出了一种基于概率电感的InduM模型来降低芯片间通信的时序延迟。InduM的主要优点是:1)在模型中考虑了电感效应;2)基于5线制,精度更高;3)可适用于任意宽度的通信信道。为了验证所提出的模型,在不同的工作条件下进行了SPICE仿真,并将仿真得到的延迟与InduM模型的结果进行了比较。比较表明,该算法可以有效地估计通信信道的时延,误差率为4 ~ 5%。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
InduM: An Accurate probablity Inductance-based Model to Predict Delay in Chips
The reliability in many-core and multicore systems is dependent on the correct functionality of communication structure between cores. However, data transfer between cores in these on chip communications can seriously face with crosstalk faults. Timing delay is the most effect of crosstalk faults and so providing a model to predict the delay can reduce the time for designers to provide more efficient mechanisms to decrease crosstalk faults. Accordingly, this paper proposes a probability inductance-based model named InduM to reduce the timing delay in the communication of chips. The main advantages of InduM are: 1) it considers the inductance effects in the model;2) it is based on 5-wire that is more accurate 3) it can be applied to a communication channel with any arbitrary width. To validate the proposed model, SPICE simulations are performed in a various working conditions and delays obtained from simulations compared with those resulting from InduM model. Comparisons show that InduM can efficiently estimate the delay of communication channels with 4-5 % error rate.
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