基于开关电容积分器(130nm)的一阶Sigma-Delta调制器设计与分析

2021 International Conference on Innovative Computing, Intelligent Communication and Smart Electrical Systems (ICSES) Pub Date : 2021-09-24 DOI:10.1109/ICSES52305.2021.9633907

Mikhili Murali Krishna, M. Vadivel

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引用次数: 0

摘要

现代世界数字化发展迅速。然而，现实世界是模拟的，需要一个足够的转换器。本文设计并分析了这种模数调制器。ΣΔ-modulator继承了一个OTAas作为主块。其中调制器是一个离散时间开关电容积分器，离散时间低通积分器和双尾比较器作为1位ADC/量化器获得一阶噪声整形调制器。该调制器采用0.13um CMOS技术，使用1.3v电源电压。得到该调制器的SFDR为72.58dB, THD为0.489，总功耗(不包括d型翻转)为1.147mw。

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Design and Analysis of First Order Sigma-Delta Modulator Based on Switched Capacitor Integrator (130nm)

The modern world is digitally advancing rapidly. However, the real world is analog which requires an adequate converter. The analysis of Such an Analog-to-digital modulator is designed and presented in this paper. The ΣΔ-modulator inherits an OTAas the main block. Where the modulator is a discrete-time switched capacitor integrator, Discrete-time low pass integrator and a double tail comparator as 1-bit ADC/quantizer obtain a first-order noise shaping modulator. The modulator implemented at 0.13um CMOS technology using 1.3v supply voltage. That obtained the SFDR of 72.58dB, THD of 0.489 and overall power dissipation (excluding D-flip flips) of the modulator is 1.147mw.

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2021 International Conference on Innovative Computing, Intelligent Communication and Smart Electrical Systems (ICSES)

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