基于结构方法的IP块识别算法

Anna Shubnaya, M. Shupletsov
{"title":"基于结构方法的IP块识别算法","authors":"Anna Shubnaya, M. Shupletsov","doi":"10.1109/EICONRUS.2019.8656919","DOIUrl":null,"url":null,"abstract":"Technology mapping for macroblocks is a problem of implementing subcircuits in a Boolean circuit with predesigned IP blocks, like multiplexers and arithmetic circuits. In this paper, we propose algorithms for identifying some special kinds of macroblocks in an arbitrary Boolean circuit using dynamic programming and structural approach. Our algorithms can identify n-input standard gates (and-gates, or-gates, xor-gates, nand-gates, nor-gates and xnor-gates) with a large input size n. Also multiplexers and multiplexer buses can be identified using our algorithms.Proposed algorithms were implemented in a C++ programming language. It can identify and substitute specified macroblocks into a Boolean circuit represented in Verilog HDL format. Algorithms were tested on benchmarks from ICCAD- 2013 contest, where similar problem was introduced, and ISCAS- 85 benchmarks were also used to test our algorithms.","PeriodicalId":6748,"journal":{"name":"2019 IEEE Conference of Russian Young Researchers in Electrical and Electronic Engineering (EIConRus)","volume":"2 1","pages":"1672-1677"},"PeriodicalIF":0.0000,"publicationDate":"2019-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"2","resultStr":"{\"title\":\"Algorithms for IP Block Identification Based on Structural Approach\",\"authors\":\"Anna Shubnaya, M. Shupletsov\",\"doi\":\"10.1109/EICONRUS.2019.8656919\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Technology mapping for macroblocks is a problem of implementing subcircuits in a Boolean circuit with predesigned IP blocks, like multiplexers and arithmetic circuits. In this paper, we propose algorithms for identifying some special kinds of macroblocks in an arbitrary Boolean circuit using dynamic programming and structural approach. Our algorithms can identify n-input standard gates (and-gates, or-gates, xor-gates, nand-gates, nor-gates and xnor-gates) with a large input size n. Also multiplexers and multiplexer buses can be identified using our algorithms.Proposed algorithms were implemented in a C++ programming language. It can identify and substitute specified macroblocks into a Boolean circuit represented in Verilog HDL format. Algorithms were tested on benchmarks from ICCAD- 2013 contest, where similar problem was introduced, and ISCAS- 85 benchmarks were also used to test our algorithms.\",\"PeriodicalId\":6748,\"journal\":{\"name\":\"2019 IEEE Conference of Russian Young Researchers in Electrical and Electronic Engineering (EIConRus)\",\"volume\":\"2 1\",\"pages\":\"1672-1677\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2019-01-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"2\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2019 IEEE Conference of Russian Young Researchers in Electrical and Electronic Engineering (EIConRus)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/EICONRUS.2019.8656919\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2019 IEEE Conference of Russian Young Researchers in Electrical and Electronic Engineering (EIConRus)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/EICONRUS.2019.8656919","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 2

摘要

宏块的技术映射是在布尔电路中使用预先设计的IP块(如多路复用器和算术电路)实现子电路的问题。本文提出了一种利用动态规划和结构方法识别任意布尔电路中某些特殊类型宏块的算法。我们的算法可以识别具有大输入尺寸n的n个输入标准门(与门,或门,异或门,与门,无门和异或门)。也可以使用我们的算法识别多路复用器和多路复用器总线。提出的算法在c++编程语言中实现。它可以识别并将指定的宏块替换成用Verilog HDL格式表示的布尔电路。算法在ICCAD- 2013竞赛的基准测试上进行了测试,其中引入了类似的问题,ISCAS- 85基准测试也用于测试我们的算法。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
Algorithms for IP Block Identification Based on Structural Approach
Technology mapping for macroblocks is a problem of implementing subcircuits in a Boolean circuit with predesigned IP blocks, like multiplexers and arithmetic circuits. In this paper, we propose algorithms for identifying some special kinds of macroblocks in an arbitrary Boolean circuit using dynamic programming and structural approach. Our algorithms can identify n-input standard gates (and-gates, or-gates, xor-gates, nand-gates, nor-gates and xnor-gates) with a large input size n. Also multiplexers and multiplexer buses can be identified using our algorithms.Proposed algorithms were implemented in a C++ programming language. It can identify and substitute specified macroblocks into a Boolean circuit represented in Verilog HDL format. Algorithms were tested on benchmarks from ICCAD- 2013 contest, where similar problem was introduced, and ISCAS- 85 benchmarks were also used to test our algorithms.
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