An Arbitrary-Resampling-based synchrophasor measurement algorithm in compliance with IEEE Std C37.118.1a-2014: Design, implementation, and validation

Synchrophasor technology is undergoing rapid changes due to the release of a new standard IEEE Std C37.118.1-2011 and its corresponding amendment IEEE Std C37.118.1a-2014. At present, few Phasor Measurement Units (PMUs) in the market can satisfy all requirements specified in IEEE Std C37.118.1a-2014. To fill this gap, this paper proposes a novel Arbitrary-Resampling-based algorithm for synchrophasor measurement. The proposed algorithm resamples even-time input signals to even-angle signals by measuring the instantaneous signal frequency, which ensures that sample number is the same in each cycle. Further processing can be performed on the resampled signals to precisely measure the magnitude and phase values of the fundamental components. The proposed algorithm is successfully implemented on a Field Programmable Gate Array (FPGA)-based target. Besides, this paper also provides the test results for the compliance tests specified in IEEE Std C37.118.1a-2014, which show that the proposed algorithm is compliant with the standard.