一个7b, 3.75ps分辨率的65纳米CMOS两步时间-数字转换器，使用脉冲序列时间放大器

2012 Symposium on VLSI Circuits (VLSIC) Pub Date : 2012-06-13 DOI:10.1109/VLSIC.2012.6243855

KwangSeok Kim, Young-Hwa Kim, Wonsik Yu, Seonghwan Cho

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引用次数: 55

摘要

提出了一种采用新型脉冲串时间放大器的时间-数字转换器(TDC)。所提出的TDC利用具有门控延迟线的重复脉冲进行免校准和可编程的时间放大和量化。利用该电路实现了一个7位两步时间-数字转换器。采用65nm CMOS工艺制作的原型芯片在200Msps下，功耗3.6mW，占用0.02mm2，时间分辨率为3.75ps。

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A 7b, 3.75ps resolution two-step time-to-digital converter in 65nm CMOS using pulse-train time amplifier

This paper presents a time-to-digital converter (TDC) using a novel pulse-train time amplifier. The proposed TDC exploits repetitive pulses with gated delay-lines for a calibration-free and programmable time amplification and quantization. Using this circuit, a 7-bit two-step time-to-digital converter is implemented. The prototype chip fabricated in 65nm CMOS process achieves 3.75ps of time resolution at 200Msps while consuming 3.6mW and occupying 0.02mm2.

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2012 Symposium on VLSI Circuits (VLSIC)

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