142 dB /spl Delta//spl Sigma/ ADC, LSB为100 nV，采用3v CMOS工艺

Proceedings of the IEEE 2000 Custom Integrated Circuits Conference (Cat. No.00CH37044) Pub Date : 2000-05-21 DOI:10.1109/CICC.2000.852606

R. Naiknaware, T. Fiez

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引用次数: 9

摘要

采用0.6 /spl mu/m CMOS工艺设计的A /spl Delta//spl Sigma/ ADC，参考电压仅为1.0 V，在100 Hz和1000 Hz带宽下分别提供142 dB和132 dB的动态范围。采用降噪策略实现的功率优化ADC的本底噪声为-168 dB，相当于1 k/spl ω /电阻的噪声。没有降噪机制的参考ADC的本底噪声为-148 dB。高分辨率转换器的目标是用于敏感仪器，如远程地震监测和生物医学设备，从单个3.0 V电源消耗22.8 mW。

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142 dB /spl Delta//spl Sigma/ ADC with a 100 nV LSB in a 3 V CMOS process

A /spl Delta//spl Sigma/ ADC designed in a 0.6 /spl mu/m CMOS process uses a reference voltage of only 1.0 V to provide a dynamic range of 142 dB and 132 dB in a bandwidth of 100 and 1000 Hz, respectively. The power optimized ADC implemented using a noise cancellation strategy has a noise floor of -168 dB, equivalent to the noise of a 1 k/spl Omega/ resistor. A reference ADC designed without a noise reduction mechanism has a noise floor of -148 dB. The high resolution converter targeted for sensitive instrumentation such as remote seismic monitoring and biomedical devices consumes 22.8 mW from a single 3.0 V supply.

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Proceedings of the IEEE 2000 Custom Integrated Circuits Conference (Cat. No.00CH37044)

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