基于JESD204B协议的链路层设计与实现

2021 11th International Conference on Information Technology in Medicine and Education (ITME) Pub Date : 2021-11-01 DOI:10.1109/ITME53901.2021.00021

Xuming Wang, Gang Yang

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引用次数: 1

摘要

接口协议JESD204B支持12.5 Gbit/s的串行传输速率，可以解决数据转换器与逻辑器件之间的高速数据传输问题。本文采用Verilog HDL设计了基于JESD204B协议的发送端和接收端链路层，并通过Xilinx ZYNQ7000系列开发板和AD9375射频板验证了设计的可行性。综合结果表明，该方案实现的数据链路层能够满足协议要求，实现数据的正常传输，并大大降低了资源的消耗。它具有通用性和可移植性的特点。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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Design and Implementation of Link Layer Based on JESD204B Protocol

Interface protocol JESD204B can support 12.5 Gbit/s serial transmission rate, which can solve the problem of high-speed data transmission between data converter and logic device. In this paper, the link layer of sender and receiver based on JESD204B protocol is designed with Verilog HDL, and the feasibility of the design is verified by Xilinx ZYNQ7000 series development board and AD9375 rf board. The comprehensive results show that the data link layer implemented in this scheme can meet the protocol requirements, realize the normal transmission of data, and greatly reduce the consumption of resources. It has the characteristics of universality and portability.

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来源期刊

2021 11th International Conference on Information Technology in Medicine and Education (ITME)

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