Neurocube:一个具有高密度三维存储器的可编程数字神经形态架构

Duckhwan Kim, J. Kung, S. Chai, S. Yalamanchili, S. Mukhopadhyay
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引用次数: 355

摘要

本文提出了一种基于三维高密度存储器集成逻辑层的可编程、可扩展的数字神经形态体系结构,用于高效的神经计算。所提出的架构由处理引擎集群组成,通过二维网格网络作为处理层连接,该处理层与多层DRAM集成在3D中。PE集群并行访问多个内存通道(vault)。这种操作原理称为以内存为中心的计算,它在HMC的vault控制器中嵌入专门的状态机,将数据驱动到PE集群中。本文介绍了Neurocube的基本架构,并分析了28nm和15nm工艺合成的逻辑层。通过卷积神经网络的映射以及对训练和推理的后续功率和性能的估计,对Neurocube的性能进行了评估和说明。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
Neurocube: A Programmable Digital Neuromorphic Architecture with High-Density 3D Memory
This paper presents a programmable and scalable digital neuromorphic architecture based on 3D high-density memory integrated with logic tier for efficient neural computing. The proposed architecture consists of clusters of processing engines, connected by 2D mesh network as a processing tier, which is integrated in 3D with multiple tiers of DRAM. The PE clusters access multiple memory channels (vaults) in parallel. The operating principle, referred to as the memory centric computing, embeds specialized state-machines within the vault controllers of HMC to drive data into the PE clusters. The paper presents the basic architecture of the Neurocube and an analysis of the logic tier synthesized in 28nm and 15nm process technologies. The performance of the Neurocube is evaluated and illustrated through the mapping of a Convolutional Neural Network and estimating the subsequent power and performance for both training and inference.
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