理解和减少高密度DDR4 DRAM系统中的刷新开销

Janani Mukundan, H. Hunter, Kyu-hyoun Kim, Jeffrey Stuecheli, José F. Martínez
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引用次数: 103

摘要

最近的DRAM规范显示刷新延迟增加。刷新命令阻塞了一个满秩,显著降低了内存子系统中的可用并行性,从而降低了性能。细粒度刷新(Fine Granularity Refresh, FGR)是JEDEC的DDR4 DRAM规范中最近宣布的一项功能,它试图通过创建一系列刷新选项来解决这个问题,这些选项提供了刷新延迟和频率之间的权衡。在本文中,我们首先对DDR4 DRAM的FGR特性进行了分析,并表明在各种应用中没有放之四海而皆准的选择。然后,我们介绍了自适应刷新(AR),这是一种简单而有效的机制,可以动态地为每个应用程序和应用程序中的每个阶段选择最佳的FGR模式。当更仔细地观察刷新问题时,我们在高密度DRAM系统中发现了一种我们称之为命令队列扣押的现象,即内存控制器的命令队列暂时扣押,因为它充满了要刷新的等级的命令。为了解决这个问题,我们提出了两种互补的机制,即延迟命令扩展(DCE)和抢先命令耗尽(PCD)。我们的研究结果表明,AR确实有效地利用了DDR4的FGR。然而,一旦我们提出的DCE和PCD机制被加入,DDR4的FGR在大多数情况下变得多余,除了在一些对内存高度敏感的应用程序中,使用AR确实提供了一些额外的好处。总之,我们的模拟表明,在正常(扩展)DRAM工作温度下,对于一组不同的并行应用程序,所提出的机制相对于传统刷新产生8%(14%)的平均加速。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
Understanding and mitigating refresh overheads in high-density DDR4 DRAM systems
Recent DRAM specifications exhibit increasing refresh latencies. A refresh command blocks a full rank, decreasing available parallelism in the memory subsystem significantly, thus decreasing performance. Fine Granularity Refresh (FGR) is a feature recently announced as part of JEDEC's DDR4 DRAM specification that attempts to tackle this problem by creating a range of refresh options that provide a trade-off between refresh latency and frequency. In this paper, we first conduct an analysis of DDR4 DRAM's FGR feature, and show that there is no one-size-fits-all option across a variety of applications. We then present Adaptive Refresh (AR), a simple yet effective mechanism that dynamically chooses the best FGR mode for each application and phase within the application. When looking at the refresh problem more closely, we identify in high-density DRAM systems a phenomenon that we call command queue seizure, whereby the memory controller's command queue seizes up temporarily because it is full with commands to a rank that is being refreshed. To attack this problem, we propose two complementary mechanisms called Delayed Command Expansion (DCE) and Preemptive Command Drain (PCD). Our results show that AR does exploit DDR4's FGR effectively. However, once our proposed DCE and PCD mechanisms are added, DDR4's FGR becomes redundant in most cases, except in a few highly memory-sensitive applications, where the use of AR does provide some additional benefit. In all, our simulations show that the proposed mechanisms yield 8% (14%) mean speedup with respect to traditional refresh, at normal (extended) DRAM operating temperatures, for a set of diverse parallel applications.
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