基于CLIC扩展的嵌入式RISC-V处理器快速中断系统

B. Mao, N. Tan, Ting Chong, Lei Li
{"title":"基于CLIC扩展的嵌入式RISC-V处理器快速中断系统","authors":"B. Mao, N. Tan, Ting Chong, Lei Li","doi":"10.1109/ICICM54364.2021.9660345","DOIUrl":null,"url":null,"abstract":"A fast interrupt response time is a very important feature for embedded processors. In this paper, we design a fast interrupt system for embedded RISC-V processors. It is further extended on the Core-Local Interrupt Controller (CLIC) based interrupt system. When an interrupt happens, the general-purpose registers and other interrupt related registers such as Control and Status Registers (CSRs) are pushed to the stack memory automatically. Thus, there is no additional software overhead in the Interrupt Service Routine (ISR), and the real handler code can be executed immediately. The interrupt response time of the interrupt system based on the CLIC extension is shorter than that of a RISC-V processor only employing the CLIC, and is comparable to that of an ARM}","PeriodicalId":6693,"journal":{"name":"2021 6th International Conference on Integrated Circuits and Microsystems (ICICM)","volume":"55 1","pages":"109-113"},"PeriodicalIF":0.0000,"publicationDate":"2021-10-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"2","resultStr":"{\"title\":\"A CLIC Extension Based Fast Interrupt System for Embedded RISC-V Processors\",\"authors\":\"B. Mao, N. Tan, Ting Chong, Lei Li\",\"doi\":\"10.1109/ICICM54364.2021.9660345\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A fast interrupt response time is a very important feature for embedded processors. In this paper, we design a fast interrupt system for embedded RISC-V processors. It is further extended on the Core-Local Interrupt Controller (CLIC) based interrupt system. When an interrupt happens, the general-purpose registers and other interrupt related registers such as Control and Status Registers (CSRs) are pushed to the stack memory automatically. Thus, there is no additional software overhead in the Interrupt Service Routine (ISR), and the real handler code can be executed immediately. The interrupt response time of the interrupt system based on the CLIC extension is shorter than that of a RISC-V processor only employing the CLIC, and is comparable to that of an ARM}\",\"PeriodicalId\":6693,\"journal\":{\"name\":\"2021 6th International Conference on Integrated Circuits and Microsystems (ICICM)\",\"volume\":\"55 1\",\"pages\":\"109-113\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2021-10-22\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"2\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2021 6th International Conference on Integrated Circuits and Microsystems (ICICM)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ICICM54364.2021.9660345\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2021 6th International Conference on Integrated Circuits and Microsystems (ICICM)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICICM54364.2021.9660345","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 2

摘要

快速的中断响应时间是嵌入式处理器的一个非常重要的特性。本文设计了一种嵌入式RISC-V处理器的快速中断系统。它在基于核心局部中断控制器(CLIC)的中断系统上得到进一步扩展。当中断发生时,通用寄存器和其他与中断相关的寄存器,如控制寄存器和状态寄存器(csr)被自动推送到堆栈内存中。因此,在中断服务例程(ISR)中没有额外的软件开销,并且可以立即执行真正的处理程序代码。基于CLIC扩展的中断系统的中断响应时间比仅采用CLIC的RISC-V处理器短,与ARM处理器相当。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
A CLIC Extension Based Fast Interrupt System for Embedded RISC-V Processors
A fast interrupt response time is a very important feature for embedded processors. In this paper, we design a fast interrupt system for embedded RISC-V processors. It is further extended on the Core-Local Interrupt Controller (CLIC) based interrupt system. When an interrupt happens, the general-purpose registers and other interrupt related registers such as Control and Status Registers (CSRs) are pushed to the stack memory automatically. Thus, there is no additional software overhead in the Interrupt Service Routine (ISR), and the real handler code can be executed immediately. The interrupt response time of the interrupt system based on the CLIC extension is shorter than that of a RISC-V processor only employing the CLIC, and is comparable to that of an ARM}
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