Ying Liu, Zhixuan Wang, W. He, Linxiao Shen, Yihan Zhang, Peiyu Chen, Meng Wu, Hao Zhang, Peng Zhou, Jinguang Liu, Guangyu Sun, Jiayoon Ru, Le Ye, Ru Huang
{"title":"基于终极事件驱动仿生结构和内存计算技术的82nW 0.53pJ/SOP无时钟脉冲神经网络,具有40µs延迟,可用于AloT唤醒功能","authors":"Ying Liu, Zhixuan Wang, W. He, Linxiao Shen, Yihan Zhang, Peiyu Chen, Meng Wu, Hao Zhang, Peng Zhou, Jinguang Liu, Guangyu Sun, Jiayoon Ru, Le Ye, Ru Huang","doi":"10.1109/ISSCC42614.2022.9731795","DOIUrl":null,"url":null,"abstract":"Human brain is a natural ultimate-event-driven (UED) system with low power and real-time response-ability, thanks to the asynchronous propagation and processing of spikes. Power dissipation and latency are major concerns in AloT devices, usually operating in random-sparse-event (RSE) scenarios (Fig. 22.7.1, top). Being event-driven on the system level, an always-on wake-up system (WUS) detects the valid RSEs energy-efficiently and intelligently, and upon detection turns on the power-hungry high-performance system (HPS). Being event-driven on the module level, a prior WUS [1] uses asynchronous feature extraction and synchronous convolutional neural network to detect the RSEs, consuming 148nW-to-1.68µW with 348ms latency. On the circuit level, the Spiking Neural Network (SNN) gives natural event-driven property. However, the prior SNN works did not fully explore this nature. An SNN circuit [2] achieves keyword spotting task at 205nW-to-570nW, but the framing method causes 100ms latency and is not true real-time. The SNN core in [5] uses synchronous digital design, which consumes significant power by the clock tree. The asynchronous-in-global synchronous-in-local [3]–[4] SNN circuits use local clock signals. They need arbiters in each layer to sort the spikes, weakening the parallelism and timing; additionally, the separation of storage and computing consumes more energy for data movement.","PeriodicalId":6830,"journal":{"name":"2022 IEEE International Solid- State Circuits Conference (ISSCC)","volume":"32 1","pages":"372-374"},"PeriodicalIF":0.0000,"publicationDate":"2022-02-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"13","resultStr":"{\"title\":\"An 82nW 0.53pJ/SOP Clock-Free Spiking Neural Network with 40µs Latency for AloT Wake-Up Functions Using Ultimate-Event-Driven Bionic Architecture and Computing-in-Memory Technique\",\"authors\":\"Ying Liu, Zhixuan Wang, W. He, Linxiao Shen, Yihan Zhang, Peiyu Chen, Meng Wu, Hao Zhang, Peng Zhou, Jinguang Liu, Guangyu Sun, Jiayoon Ru, Le Ye, Ru Huang\",\"doi\":\"10.1109/ISSCC42614.2022.9731795\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Human brain is a natural ultimate-event-driven (UED) system with low power and real-time response-ability, thanks to the asynchronous propagation and processing of spikes. Power dissipation and latency are major concerns in AloT devices, usually operating in random-sparse-event (RSE) scenarios (Fig. 22.7.1, top). Being event-driven on the system level, an always-on wake-up system (WUS) detects the valid RSEs energy-efficiently and intelligently, and upon detection turns on the power-hungry high-performance system (HPS). Being event-driven on the module level, a prior WUS [1] uses asynchronous feature extraction and synchronous convolutional neural network to detect the RSEs, consuming 148nW-to-1.68µW with 348ms latency. On the circuit level, the Spiking Neural Network (SNN) gives natural event-driven property. However, the prior SNN works did not fully explore this nature. An SNN circuit [2] achieves keyword spotting task at 205nW-to-570nW, but the framing method causes 100ms latency and is not true real-time. The SNN core in [5] uses synchronous digital design, which consumes significant power by the clock tree. The asynchronous-in-global synchronous-in-local [3]–[4] SNN circuits use local clock signals. They need arbiters in each layer to sort the spikes, weakening the parallelism and timing; additionally, the separation of storage and computing consumes more energy for data movement.\",\"PeriodicalId\":6830,\"journal\":{\"name\":\"2022 IEEE International Solid- State Circuits Conference (ISSCC)\",\"volume\":\"32 1\",\"pages\":\"372-374\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2022-02-20\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"13\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2022 IEEE International Solid- State Circuits Conference (ISSCC)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ISSCC42614.2022.9731795\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2022 IEEE International Solid- State Circuits Conference (ISSCC)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ISSCC42614.2022.9731795","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
An 82nW 0.53pJ/SOP Clock-Free Spiking Neural Network with 40µs Latency for AloT Wake-Up Functions Using Ultimate-Event-Driven Bionic Architecture and Computing-in-Memory Technique
Human brain is a natural ultimate-event-driven (UED) system with low power and real-time response-ability, thanks to the asynchronous propagation and processing of spikes. Power dissipation and latency are major concerns in AloT devices, usually operating in random-sparse-event (RSE) scenarios (Fig. 22.7.1, top). Being event-driven on the system level, an always-on wake-up system (WUS) detects the valid RSEs energy-efficiently and intelligently, and upon detection turns on the power-hungry high-performance system (HPS). Being event-driven on the module level, a prior WUS [1] uses asynchronous feature extraction and synchronous convolutional neural network to detect the RSEs, consuming 148nW-to-1.68µW with 348ms latency. On the circuit level, the Spiking Neural Network (SNN) gives natural event-driven property. However, the prior SNN works did not fully explore this nature. An SNN circuit [2] achieves keyword spotting task at 205nW-to-570nW, but the framing method causes 100ms latency and is not true real-time. The SNN core in [5] uses synchronous digital design, which consumes significant power by the clock tree. The asynchronous-in-global synchronous-in-local [3]–[4] SNN circuits use local clock signals. They need arbiters in each layer to sort the spikes, weakening the parallelism and timing; additionally, the separation of storage and computing consumes more energy for data movement.