一个2.8GS/s 44.6mW时间交错ADC，实现50.9dB SNDR和3dB有效分辨率带宽为1.5GHz

2012 Symposium on VLSI Circuits (VLSIC) Pub Date : 2012-06-13 DOI:10.1109/VLSIC.2012.6243801

D. Stepanovic, B. Nikolić

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引用次数: 52

摘要

提出了一种采用65nm CMOS芯片设计的低功耗、低面积的24路时间交错SAR ADC。在2.8GS/s采样率下，ADC从1.2V电源消耗44.6mW功率，同时实现50.9dB的峰值SNDR，并在整个第一奈奎斯特区保持高于48.2dB的SNDR。

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A 2.8GS/s 44.6mW time-interleaved ADC achieving 50.9dB SNDR and 3dB effective resolution bandwidth of 1.5GHz in 65nm CMOS

This paper presents a power- and area-efficient 24-way time-interleaved SAR ADC designed in 65nm CMOS. At 2.8GS/s sampling rate the ADC consumes 44.6mW of power from a 1.2V supply while achieving peak SNDR of 50.9dB and retaining SNDR higher than 48.2dB across the entire first Nyquist zone.

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2012 Symposium on VLSI Circuits (VLSIC)

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