用于512×512红外焦平面阵列的低功耗低温CMOS ROIC

2011 IEEE International Conference of Electron Devices and Solid-State Circuits Pub Date : 2011-12-29 DOI:10.1109/EDSSC.2011.6117641

Hongliang Zhao, Yiqiang Zhao, Yiwei Song, Jun Liao, Junfeng Geng

{"title":"用于512×512红外焦平面阵列的低功耗低温CMOS ROIC","authors":"Hongliang Zhao, Yiqiang Zhao, Yiwei Song, Jun Liao, Junfeng Geng","doi":"10.1109/EDSSC.2011.6117641","DOIUrl":null,"url":null,"abstract":"A low power cryogenic readout integrated circuit (ROIC) for mid- and far-wave infrared focal plane array (FPA) is presented as a prototype for 512×512 image system. By applying capacitive trans-impedance amplifier (CTIA) with inherent correlated double sampling (CSD) structure, a high performance readout interface circuit for the infrared FPA is realized with a pixel size of 30×30 µm2. Optimized column readout timing and two operating modes in column amplifiers are used to reduce the power consumption. The readout chip designed by Chartered 0.35 µm 2P4M process shows more than 10 MHz readout rate and less than 70 mW power consumption under 3.3 V supply voltage at 77 K to 150 K operating temperature. And it occupies an area of 18.4×17.5 mm2.","PeriodicalId":6363,"journal":{"name":"2011 IEEE International Conference of Electron Devices and Solid-State Circuits","volume":null,"pages":null},"PeriodicalIF":0.0000,"publicationDate":"2011-12-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"5","resultStr":"{\"title\":\"A low power cryogenic CMOS ROIC for 512×512 infrared focal plane array\",\"authors\":\"Hongliang Zhao, Yiqiang Zhao, Yiwei Song, Jun Liao, Junfeng Geng\",\"doi\":\"10.1109/EDSSC.2011.6117641\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A low power cryogenic readout integrated circuit (ROIC) for mid- and far-wave infrared focal plane array (FPA) is presented as a prototype for 512×512 image system. By applying capacitive trans-impedance amplifier (CTIA) with inherent correlated double sampling (CSD) structure, a high performance readout interface circuit for the infrared FPA is realized with a pixel size of 30×30 µm2. Optimized column readout timing and two operating modes in column amplifiers are used to reduce the power consumption. The readout chip designed by Chartered 0.35 µm 2P4M process shows more than 10 MHz readout rate and less than 70 mW power consumption under 3.3 V supply voltage at 77 K to 150 K operating temperature. And it occupies an area of 18.4×17.5 mm2.\",\"PeriodicalId\":6363,\"journal\":{\"name\":\"2011 IEEE International Conference of Electron Devices and Solid-State Circuits\",\"volume\":null,\"pages\":null},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2011-12-29\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"5\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2011 IEEE International Conference of Electron Devices and Solid-State Circuits\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/EDSSC.2011.6117641\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2011 IEEE International Conference of Electron Devices and Solid-State Circuits","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/EDSSC.2011.6117641","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}

引用次数: 5

摘要

提出了一种用于中远波红外焦平面阵列(FPA)的低功耗低温读出集成电路(ROIC)，作为512×512图像系统的原型。采用具有固有相关双采样(CSD)结构的电容式反阻抗放大器(CTIA)，实现了像素尺寸为30×30µm2的红外FPA的高性能读出接口电路。优化的列读出时间和两种工作模式的列放大器被用来降低功耗。采用Chartered 0.35µm 2P4M工艺设计的读出芯片在3.3 V供电电压、77 K ~ 150 K工作温度下，读出速率超过10 MHz，功耗小于70 mW。它的面积是18.4×17.5 mm2。

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A low power cryogenic CMOS ROIC for 512×512 infrared focal plane array

A low power cryogenic readout integrated circuit (ROIC) for mid- and far-wave infrared focal plane array (FPA) is presented as a prototype for 512×512 image system. By applying capacitive trans-impedance amplifier (CTIA) with inherent correlated double sampling (CSD) structure, a high performance readout interface circuit for the infrared FPA is realized with a pixel size of 30×30 µm2. Optimized column readout timing and two operating modes in column amplifiers are used to reduce the power consumption. The readout chip designed by Chartered 0.35 µm 2P4M process shows more than 10 MHz readout rate and less than 70 mW power consumption under 3.3 V supply voltage at 77 K to 150 K operating temperature. And it occupies an area of 18.4×17.5 mm2.

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来源期刊

2011 IEEE International Conference of Electron Devices and Solid-State Circuits

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