{"title":"一种改进的时钟使能低功耗计数器设计","authors":"Varsha Dewre, Rakesh Mandliya","doi":"10.9790/9622-0706065961","DOIUrl":null,"url":null,"abstract":"This paper presents an improved low power design of a 4-bit Johnson Counter which is designed using and Clock enable method. The proposed design shows a power reduction of 5mW as compared to the conventional Johnson counter which is 7mW. Pulse triggered flip flop employed in the proposed design can save power up to 28.57% as compared to the conventional design. All the simulations were carried out using Xilinx software in SIM module.","PeriodicalId":13972,"journal":{"name":"International Journal of Engineering Research and Applications","volume":null,"pages":null},"PeriodicalIF":0.0000,"publicationDate":"2017-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"An Improved Low Power Counter Design with Clock Enable\",\"authors\":\"Varsha Dewre, Rakesh Mandliya\",\"doi\":\"10.9790/9622-0706065961\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This paper presents an improved low power design of a 4-bit Johnson Counter which is designed using and Clock enable method. The proposed design shows a power reduction of 5mW as compared to the conventional Johnson counter which is 7mW. Pulse triggered flip flop employed in the proposed design can save power up to 28.57% as compared to the conventional design. All the simulations were carried out using Xilinx software in SIM module.\",\"PeriodicalId\":13972,\"journal\":{\"name\":\"International Journal of Engineering Research and Applications\",\"volume\":null,\"pages\":null},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2017-07-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"International Journal of Engineering Research and Applications\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.9790/9622-0706065961\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"International Journal of Engineering Research and Applications","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.9790/9622-0706065961","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
An Improved Low Power Counter Design with Clock Enable
This paper presents an improved low power design of a 4-bit Johnson Counter which is designed using and Clock enable method. The proposed design shows a power reduction of 5mW as compared to the conventional Johnson counter which is 7mW. Pulse triggered flip flop employed in the proposed design can save power up to 28.57% as compared to the conventional design. All the simulations were carried out using Xilinx software in SIM module.
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