{"title":"一种用于软件在线自检的处理器屏蔽","authors":"Ching-Wen Lin, C. Chen","doi":"10.1109/APCCAS.2016.7803919","DOIUrl":null,"url":null,"abstract":"Software-based processor self-test typically ignores system related testing issues such as interrupt, memory-mapped IOs, especially for on-line testing. We propose an architectural support for processor SBST testing: Processor Shield, which can tackle the difficult-to-test issues during on-line SBST. We develop an execution flow to control the processor shield and run the SBST program without interfering other processes and on-bus devices. Finally, we present a case study that executes the SBST program under Linux kernel on an ARMv5-compatible processor system. Our method can successfully switch the test process and the kernel process and achieve the expected high processor fault coverage. The hardware overhead of the processor shield is 2.6% compared to the logic part of the processor.","PeriodicalId":6495,"journal":{"name":"2016 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS)","volume":"13 5 1","pages":"149-152"},"PeriodicalIF":0.0000,"publicationDate":"2016-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":"{\"title\":\"A processor shield for software-based on-line self-test\",\"authors\":\"Ching-Wen Lin, C. Chen\",\"doi\":\"10.1109/APCCAS.2016.7803919\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Software-based processor self-test typically ignores system related testing issues such as interrupt, memory-mapped IOs, especially for on-line testing. We propose an architectural support for processor SBST testing: Processor Shield, which can tackle the difficult-to-test issues during on-line SBST. We develop an execution flow to control the processor shield and run the SBST program without interfering other processes and on-bus devices. Finally, we present a case study that executes the SBST program under Linux kernel on an ARMv5-compatible processor system. Our method can successfully switch the test process and the kernel process and achieve the expected high processor fault coverage. The hardware overhead of the processor shield is 2.6% compared to the logic part of the processor.\",\"PeriodicalId\":6495,\"journal\":{\"name\":\"2016 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS)\",\"volume\":\"13 5 1\",\"pages\":\"149-152\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2016-10-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"1\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2016 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/APCCAS.2016.7803919\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2016 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/APCCAS.2016.7803919","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A processor shield for software-based on-line self-test
Software-based processor self-test typically ignores system related testing issues such as interrupt, memory-mapped IOs, especially for on-line testing. We propose an architectural support for processor SBST testing: Processor Shield, which can tackle the difficult-to-test issues during on-line SBST. We develop an execution flow to control the processor shield and run the SBST program without interfering other processes and on-bus devices. Finally, we present a case study that executes the SBST program under Linux kernel on an ARMv5-compatible processor system. Our method can successfully switch the test process and the kernel process and achieve the expected high processor fault coverage. The hardware overhead of the processor shield is 2.6% compared to the logic part of the processor.