一种提高动态数字电路噪声容限的改进技术

2004 IEEE International Symposium on Circuits and Systems (IEEE Cat. No.04CH37512) Pub Date : 2004-05-23 DOI:10.1109/ISCAS.2004.1329315

F. Mendoza-Hernandez, M. L. Aranda, V. Champac

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引用次数: 8

摘要

由于晶体管和互连尺寸的快速缩放，VLSI电路技术正在取得令人印象深刻的进步。然而，噪声问题成为深亚微米电路的一个重要成本。本文提出了一种改进的容噪动态数字电路技术。通过电荷再分配和逻辑门内部节点的常规预充电，提高了电路的抗噪声能力。仿真结果表明，与传统的动态逻辑相比，该方法可提高8.6/spl倍/倍。

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An improved technique to increase noise-tolerance in dynamic digital circuits

Due to the rapid scaling of the transistor and interconnect dimensions the VLSI circuit technology is having an impressive advancement. However, noise issues emerge as an important cost in deep submicron circuits. In this paper we propose an improved noise-tolerant dynamic digital circuit technique. By using a charge redistribution process together with the conventional precharge of internal nodes in logic gates, the noise immunity is increased. Simulation results show an improvement of up to 8.6/spl times/over conventional dynamic logic.

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来源期刊

2004 IEEE International Symposium on Circuits and Systems (IEEE Cat. No.04CH37512)

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