{"title":"35µW 96.8dB SNDR 1 kHz BW多步增量ADC，采用多斜率扩展计数和单积分器","authors":"Yi Zhang, Chia-Hung Chen, Tao He, G. Temes","doi":"10.1109/VLSIC.2016.7573464","DOIUrl":null,"url":null,"abstract":"A multi-step incremental ADC (IADC) with multi-slope extended counting is presented. In the proposed IADC, the accuracy is enhanced by reconfiguring it as a multi-slope ADC in two additional steps. For the same accuracy, the conversion cycle is shortened by a factor of about 29 as compared to the single-step IADC. Fabricated in 0.18-μm CMOS process, the prototype ADC operates at 642 kHz and achieves a peak SNDR = 96.8 dB and DR = 99.7 dB over a 1 kHz bandwidth. The power consumption is 35 μW, which results in an excellent Schreier FoM of 174.6 dB.","PeriodicalId":6512,"journal":{"name":"2016 IEEE Symposium on VLSI Circuits (VLSI-Circuits)","volume":"22 1","pages":"1-2"},"PeriodicalIF":0.0000,"publicationDate":"2016-06-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"9","resultStr":"{\"title\":\"A 35µW 96.8dB SNDR 1 kHz BW multi-step incremental ADC using multi-slope extended counting with a single integrator\",\"authors\":\"Yi Zhang, Chia-Hung Chen, Tao He, G. Temes\",\"doi\":\"10.1109/VLSIC.2016.7573464\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A multi-step incremental ADC (IADC) with multi-slope extended counting is presented. In the proposed IADC, the accuracy is enhanced by reconfiguring it as a multi-slope ADC in two additional steps. For the same accuracy, the conversion cycle is shortened by a factor of about 29 as compared to the single-step IADC. Fabricated in 0.18-μm CMOS process, the prototype ADC operates at 642 kHz and achieves a peak SNDR = 96.8 dB and DR = 99.7 dB over a 1 kHz bandwidth. The power consumption is 35 μW, which results in an excellent Schreier FoM of 174.6 dB.\",\"PeriodicalId\":6512,\"journal\":{\"name\":\"2016 IEEE Symposium on VLSI Circuits (VLSI-Circuits)\",\"volume\":\"22 1\",\"pages\":\"1-2\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2016-06-15\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"9\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2016 IEEE Symposium on VLSI Circuits (VLSI-Circuits)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/VLSIC.2016.7573464\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2016 IEEE Symposium on VLSI Circuits (VLSI-Circuits)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/VLSIC.2016.7573464","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A 35µW 96.8dB SNDR 1 kHz BW multi-step incremental ADC using multi-slope extended counting with a single integrator
A multi-step incremental ADC (IADC) with multi-slope extended counting is presented. In the proposed IADC, the accuracy is enhanced by reconfiguring it as a multi-slope ADC in two additional steps. For the same accuracy, the conversion cycle is shortened by a factor of about 29 as compared to the single-step IADC. Fabricated in 0.18-μm CMOS process, the prototype ADC operates at 642 kHz and achieves a peak SNDR = 96.8 dB and DR = 99.7 dB over a 1 kHz bandwidth. The power consumption is 35 μW, which results in an excellent Schreier FoM of 174.6 dB.
求助内容：
应助结果提醒方式：
京公网安备 11010802042870号
