{"title":"利用蚁群算法对测试向量进行排序","authors":"Jianhua Wang, Jingbo Shao, Yingmei Li, Yuyan Huang","doi":"10.1109/ISIEA.2009.5356501","DOIUrl":null,"url":null,"abstract":"The increasing complexity of chip design has posed great challenge for low power SoC test. Test vector reordering technique can lower circuit power dissipation. This paper proposes a new approach to low power SoC test based on ant colony optimization to find the optimal orders for test vector application. Experimental results on benchmark ITC'02 demonstrate the average improvement of 12.3% over the existing methods.","PeriodicalId":6447,"journal":{"name":"2009 IEEE Symposium on Industrial Electronics & Applications","volume":"20 1","pages":"52-55"},"PeriodicalIF":0.0000,"publicationDate":"2009-12-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"8","resultStr":"{\"title\":\"Using ant colony optimization for test vector reordering\",\"authors\":\"Jianhua Wang, Jingbo Shao, Yingmei Li, Yuyan Huang\",\"doi\":\"10.1109/ISIEA.2009.5356501\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"The increasing complexity of chip design has posed great challenge for low power SoC test. Test vector reordering technique can lower circuit power dissipation. This paper proposes a new approach to low power SoC test based on ant colony optimization to find the optimal orders for test vector application. Experimental results on benchmark ITC'02 demonstrate the average improvement of 12.3% over the existing methods.\",\"PeriodicalId\":6447,\"journal\":{\"name\":\"2009 IEEE Symposium on Industrial Electronics & Applications\",\"volume\":\"20 1\",\"pages\":\"52-55\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2009-12-18\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"8\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2009 IEEE Symposium on Industrial Electronics & Applications\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ISIEA.2009.5356501\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2009 IEEE Symposium on Industrial Electronics & Applications","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ISIEA.2009.5356501","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Using ant colony optimization for test vector reordering
The increasing complexity of chip design has posed great challenge for low power SoC test. Test vector reordering technique can lower circuit power dissipation. This paper proposes a new approach to low power SoC test based on ant colony optimization to find the optimal orders for test vector application. Experimental results on benchmark ITC'02 demonstrate the average improvement of 12.3% over the existing methods.
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