{"title":"用于畸变分析的LDD MOSFET器件中与偏置相关的源漏电阻模型","authors":"Kwang-Hoon Oh, Zhiping Yu, R. Dutton","doi":"10.1109/ICVC.1999.820870","DOIUrl":null,"url":null,"abstract":"In order to describe nonlinear distortion behavior precisely, an equivalent resistance model for n/sup -/ source/drain regions of an LDD MOSFET featuring gate bias and drain bias dependence is implemented. Separating the LDD device into an intrinsic MOSFET and two buried channel (BC) MOSFETs, a resistance model has been developed in a physically consistent manner. The proposed resistance model was confirmed using 2D device simulation results and its viability for distortion analysis has been investigated.","PeriodicalId":13415,"journal":{"name":"ICVC '99. 6th International Conference on VLSI and CAD (Cat. No.99EX361)","volume":"13 1","pages":"190-193"},"PeriodicalIF":0.0000,"publicationDate":"1999-10-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"3","resultStr":"{\"title\":\"A bias dependent source/drain resistance model in LDD MOSFET devices for distortion analysis\",\"authors\":\"Kwang-Hoon Oh, Zhiping Yu, R. Dutton\",\"doi\":\"10.1109/ICVC.1999.820870\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"In order to describe nonlinear distortion behavior precisely, an equivalent resistance model for n/sup -/ source/drain regions of an LDD MOSFET featuring gate bias and drain bias dependence is implemented. Separating the LDD device into an intrinsic MOSFET and two buried channel (BC) MOSFETs, a resistance model has been developed in a physically consistent manner. The proposed resistance model was confirmed using 2D device simulation results and its viability for distortion analysis has been investigated.\",\"PeriodicalId\":13415,\"journal\":{\"name\":\"ICVC '99. 6th International Conference on VLSI and CAD (Cat. No.99EX361)\",\"volume\":\"13 1\",\"pages\":\"190-193\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1999-10-26\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"3\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"ICVC '99. 6th International Conference on VLSI and CAD (Cat. No.99EX361)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ICVC.1999.820870\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"ICVC '99. 6th International Conference on VLSI and CAD (Cat. No.99EX361)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICVC.1999.820870","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A bias dependent source/drain resistance model in LDD MOSFET devices for distortion analysis
In order to describe nonlinear distortion behavior precisely, an equivalent resistance model for n/sup -/ source/drain regions of an LDD MOSFET featuring gate bias and drain bias dependence is implemented. Separating the LDD device into an intrinsic MOSFET and two buried channel (BC) MOSFETs, a resistance model has been developed in a physically consistent manner. The proposed resistance model was confirmed using 2D device simulation results and its viability for distortion analysis has been investigated.
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