Ferri Abolhassan, R. Drefenstedt, J. Keller, W. Paul, D. Scheerer
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We sketch the physical design of a prototype of a PRAM architecture based on Ranade’s Fluent Machine. We describe a specially developed processor chip with several instruction streams and a fast butterfly connection network. For the realization of the network we consider alternatively optoelectronic and electric transmission. We also discuss some basic software issues.
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