一种使用多层实现指定延迟的时钟路由器

ICCAD. IEEE/ACM International Conference on Computer-Aided Design Pub Date : 1994-11-06 DOI:10.1109/ICCAD.1994.629782

M. Seki, Kenji Inoue, Kazuo Kato, K. Tsurusaki, S. Fukasawa, H. Sasaki, M. Aizawa

{"title":"一种使用多层实现指定延迟的时钟路由器","authors":"M. Seki, Kenji Inoue, Kazuo Kato, K. Tsurusaki, S. Fukasawa, H. Sasaki, M. Aizawa","doi":"10.1109/ICCAD.1994.629782","DOIUrl":null,"url":null,"abstract":"Clock routing to minimize the clock skew is very necessary to make high performance LSIs. Our clock routing method: (1) realizes the specified delay to each input terminal and provides a zero skew; (2) uses multiple routing layers for pin-to-pin routing; and (3) considers the delay arising from the resistance of a through-hole. Experimental results show that the delay is within 1% error compared to the specified delay and the skew can be controlled within pico second order.","PeriodicalId":90518,"journal":{"name":"ICCAD. IEEE/ACM International Conference on Computer-Aided Design","volume":"23 1","pages":"289-292"},"PeriodicalIF":0.0000,"publicationDate":"1994-11-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"6","resultStr":"{\"title\":\"A Specified Delay Accomplishing Clock Router Using Multiple Layers\",\"authors\":\"M. Seki, Kenji Inoue, Kazuo Kato, K. Tsurusaki, S. Fukasawa, H. Sasaki, M. Aizawa\",\"doi\":\"10.1109/ICCAD.1994.629782\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Clock routing to minimize the clock skew is very necessary to make high performance LSIs. Our clock routing method: (1) realizes the specified delay to each input terminal and provides a zero skew; (2) uses multiple routing layers for pin-to-pin routing; and (3) considers the delay arising from the resistance of a through-hole. Experimental results show that the delay is within 1% error compared to the specified delay and the skew can be controlled within pico second order.\",\"PeriodicalId\":90518,\"journal\":{\"name\":\"ICCAD. IEEE/ACM International Conference on Computer-Aided Design\",\"volume\":\"23 1\",\"pages\":\"289-292\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1994-11-06\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"6\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"ICCAD. IEEE/ACM International Conference on Computer-Aided Design\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ICCAD.1994.629782\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"ICCAD. IEEE/ACM International Conference on Computer-Aided Design","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICCAD.1994.629782","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}

引用次数: 6

摘要

时钟路由，以尽量减少时钟倾斜是非常必要的，使高性能的lsi。我们的时钟路由方法:(1)实现对每个输入端的指定延迟，并提供零倾斜;(2)采用多路由层进行引脚到引脚路由;(3)考虑通孔阻力引起的延迟。实验结果表明，该系统的延迟与指定延迟的误差在1%以内，偏差可以控制在皮秒级以内。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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A Specified Delay Accomplishing Clock Router Using Multiple Layers

Clock routing to minimize the clock skew is very necessary to make high performance LSIs. Our clock routing method: (1) realizes the specified delay to each input terminal and provides a zero skew; (2) uses multiple routing layers for pin-to-pin routing; and (3) considers the delay arising from the resistance of a through-hole. Experimental results show that the delay is within 1% error compared to the specified delay and the skew can be controlled within pico second order.

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ICCAD. IEEE/ACM International Conference on Computer-Aided Design

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