{"title":"使用其参数化模块布局结构的模拟布局地板规划器","authors":"Young Soo Kim, K. Yoon","doi":"10.1109/APCAS.1996.569299","DOIUrl":null,"url":null,"abstract":"This paper presents an analog layout floorplanner whose module library is parameterized with its layout structure. The developed floorplanner employs the parameterized layout template that enhances the CIF (Caltech Intermediate Form) description language. By utilizing this template, the complexity of the generator text is reduced, and an additional complex parser and analyzer are not required. This floorplanner has been tested on several benchmark circuits and displayed six to ten times of generator text reduction.","PeriodicalId":20507,"journal":{"name":"Proceedings of APCCAS'96 - Asia Pacific Conference on Circuits and Systems","volume":null,"pages":null},"PeriodicalIF":0.0000,"publicationDate":"1996-11-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"An analog layout floorplanner using its parameterized module layout structure\",\"authors\":\"Young Soo Kim, K. Yoon\",\"doi\":\"10.1109/APCAS.1996.569299\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This paper presents an analog layout floorplanner whose module library is parameterized with its layout structure. The developed floorplanner employs the parameterized layout template that enhances the CIF (Caltech Intermediate Form) description language. By utilizing this template, the complexity of the generator text is reduced, and an additional complex parser and analyzer are not required. This floorplanner has been tested on several benchmark circuits and displayed six to ten times of generator text reduction.\",\"PeriodicalId\":20507,\"journal\":{\"name\":\"Proceedings of APCCAS'96 - Asia Pacific Conference on Circuits and Systems\",\"volume\":null,\"pages\":null},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1996-11-18\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Proceedings of APCCAS'96 - Asia Pacific Conference on Circuits and Systems\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/APCAS.1996.569299\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings of APCCAS'96 - Asia Pacific Conference on Circuits and Systems","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/APCAS.1996.569299","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
An analog layout floorplanner using its parameterized module layout structure
This paper presents an analog layout floorplanner whose module library is parameterized with its layout structure. The developed floorplanner employs the parameterized layout template that enhances the CIF (Caltech Intermediate Form) description language. By utilizing this template, the complexity of the generator text is reduced, and an additional complex parser and analyzer are not required. This floorplanner has been tested on several benchmark circuits and displayed six to ten times of generator text reduction.
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