低功耗数字控制延迟插入单元和1%精度100MHz振荡器，用于DC-DC转换器的精确死区插入

ESSCIRC Conference 2015 - 41st European Solid-State Circuits Conference (ESSCIRC) Pub Date : 2015-11-02 DOI:10.1109/ESSCIRC.2015.7313910

Dmytro Cherniak, Michael Aichner, R. Nonis, N. D. Dalt

{"title":"低功耗数字控制延迟插入单元和1%精度100MHz振荡器，用于DC-DC转换器的精确死区插入","authors":"Dmytro Cherniak, Michael Aichner, R. Nonis, N. D. Dalt","doi":"10.1109/ESSCIRC.2015.7313910","DOIUrl":null,"url":null,"abstract":"This paper presents a digitally controlled delay insertion unit (DIU) for precise dead-time insertion in DC-DC converters. A fundamental building block is the 100MHz relaxation oscillator with better than +/-1% frequency accuracy in the temperature range from -40C to +150C, which is introduced for the first time with such accuracy in this frequency range. The DIU is capable of up to 32ns delay generation with 500ps step size. It is implemented in 130nm CMOS, occupies 0.098mm2 and consumes 0.45mW in ultra-low power mode.","PeriodicalId":11845,"journal":{"name":"ESSCIRC Conference 2015 - 41st European Solid-State Circuits Conference (ESSCIRC)","volume":null,"pages":null},"PeriodicalIF":0.0000,"publicationDate":"2015-11-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"2","resultStr":"{\"title\":\"Low power digitally controlled delay insertion unit and 1% accuracy 100MHz oscillator for precise dead-time insertion in DC-DC converters\",\"authors\":\"Dmytro Cherniak, Michael Aichner, R. Nonis, N. D. Dalt\",\"doi\":\"10.1109/ESSCIRC.2015.7313910\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This paper presents a digitally controlled delay insertion unit (DIU) for precise dead-time insertion in DC-DC converters. A fundamental building block is the 100MHz relaxation oscillator with better than +/-1% frequency accuracy in the temperature range from -40C to +150C, which is introduced for the first time with such accuracy in this frequency range. The DIU is capable of up to 32ns delay generation with 500ps step size. It is implemented in 130nm CMOS, occupies 0.098mm2 and consumes 0.45mW in ultra-low power mode.\",\"PeriodicalId\":11845,\"journal\":{\"name\":\"ESSCIRC Conference 2015 - 41st European Solid-State Circuits Conference (ESSCIRC)\",\"volume\":null,\"pages\":null},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2015-11-02\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"2\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"ESSCIRC Conference 2015 - 41st European Solid-State Circuits Conference (ESSCIRC)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ESSCIRC.2015.7313910\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"ESSCIRC Conference 2015 - 41st European Solid-State Circuits Conference (ESSCIRC)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ESSCIRC.2015.7313910","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}

引用次数: 2

摘要

本文提出了一种用于DC-DC变换器死区精确插入的数字控制延迟插入单元(DIU)。一个基本的组成部分是100MHz弛豫振荡器，在-40℃至+150℃的温度范围内，频率精度优于+/-1%，这是第一次在这个频率范围内以这样的精度推出。DIU能够以500ps的步长产生高达32ns的延迟。它采用130nm CMOS实现，在超低功耗模式下占地0.098mm2，功耗0.45mW。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

查看原文本刊更多论文

Low power digitally controlled delay insertion unit and 1% accuracy 100MHz oscillator for precise dead-time insertion in DC-DC converters

This paper presents a digitally controlled delay insertion unit (DIU) for precise dead-time insertion in DC-DC converters. A fundamental building block is the 100MHz relaxation oscillator with better than +/-1% frequency accuracy in the temperature range from -40C to +150C, which is introduced for the first time with such accuracy in this frequency range. The DIU is capable of up to 32ns delay generation with 500ps step size. It is implemented in 130nm CMOS, occupies 0.098mm2 and consumes 0.45mW in ultra-low power mode.

求助全文

通过发布文献求助，成功后即可免费获取论文全文。去求助

来源期刊

ESSCIRC Conference 2015 - 41st European Solid-State Circuits Conference (ESSCIRC)

自引率

0.00%

发文量