采用阶梯SC网络电容辅助双电感滤波的2.5-5MHz 87%峰值效率48v - 1v集成混合DC-DC变换器

Chen Chen, Jin Liu, Hoi Lee
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引用次数: 7

摘要

随着大数据分析的快速发展,非隔离48v到1v转换器提供了一个有竞争力的选择,以支持cpu和内存不断增加的功耗。传统降压(CB)变换器为了实现较小的输出输入转换比(CR),其导通时间极短,限制了高频工作,造成了较大的功率损耗。虽然具有较低额定电压器件的开关电容器(SC)变换器可以按比例降低高输入电压$\mathsf{V}_{\mathsf{lN}}$,但只有在固定转换比下才能实现高效率。因此,近年来出现了混合变换器,它结合了CB变换器和SC变换器的优点。飞电容多电平(FCML)[1]和混合Dickson (HD)[2]等变换器拓扑在SC网络后采用外置输出LC滤波器实现连续变幅。然而,由于[1]和[2]中的飞行电容在稳态时需要适当的电压平衡,因此在小CR条件下,当变换器需要平衡增加的飞行电容数量时,开关频率$\mathsf{f}_{\mathsf{SW}}$可以显著降低。双降压(DSD)[3]和三态DSD[4]拓扑都可以通过使用两个电感器使$\mathsf{f}_{\mathsf{SW}}$加倍,但它们的CR仅为$\mathsf{D}/2$,这限制了它们支持48v到1v转换的能力。虽然12电平串联电容变换器[5]拓扑显著降低了CR,但它需要11个飞行电容器和一个$\mathsf{GaN}$ FET作为外部元件。该转换器还具有24个片上功率晶体管,支持12相操作,从而产生较大的芯片面积。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
A 2.5-5MHz 87% Peak Efficiency 48V-to-1V Integrated Hybrid DC-DC Converter Adopting Ladder SC Network with Capacitor-Assisted Dual-Inductor Filtering
With the rapid developments in big data analytics, non-isolated 48V-to-1V converters offer a competitive choice to support the increased power consumptions in CPUs and memories. For realizing a small output-to-input conversion ratio (CR), the conventional buck (CB) converters suffer from extremely short switch on-time that limits high-frequency operation and incurs high power losses. Although the switched-capacitor (SC) converters with lower voltage rating devices can scale down the high input voltage, $\mathsf{V}_{\mathsf{lN}}$, high efficiency can only be achieved under fixed conversion ratios. Hybrid converters are thus emerged recently to combine the advantages of CB and SC converters. Converter topologies such as flying-capacitor multi-level (FCML) [1] and hybrid Dickson (HD) [2] adopt an external output LC filter after the SC network to realize continuous conversion range. However, since flying capacitor in [1] and [2] requires proper voltage balancing in the steady state, the switching frequency, $\mathsf{f}_{\mathsf{SW}}$, can be significantly slowed down when the converter needs to balance an increased number of the flying capacitor under small CR condition. Both double step-down (DSD) [3] and tri-state DSD [4] topologies can double $\mathsf{f}_{\mathsf{SW}}$ by using two inductors, but their CR is only $\mathsf{D}/2$ that limits their capability to support 48V-to-1V conversions. Although the 12-level series-capacitor converter [5] topology significantly decreases the CR, it requires 11 flying capacitors and a $\mathsf{GaN}$ FET as external components. The converter also has 24 on-chip power transistors to support 12-phase operation, resulting in a large chip area.
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