{"title":"采用阶梯SC网络电容辅助双电感滤波的2.5-5MHz 87%峰值效率48v - 1v集成混合DC-DC变换器","authors":"Chen Chen, Jin Liu, Hoi Lee","doi":"10.1109/ISSCC42614.2022.9731764","DOIUrl":null,"url":null,"abstract":"With the rapid developments in big data analytics, non-isolated 48V-to-1V converters offer a competitive choice to support the increased power consumptions in CPUs and memories. For realizing a small output-to-input conversion ratio (CR), the conventional buck (CB) converters suffer from extremely short switch on-time that limits high-frequency operation and incurs high power losses. Although the switched-capacitor (SC) converters with lower voltage rating devices can scale down the high input voltage, $\\mathsf{V}_{\\mathsf{lN}}$, high efficiency can only be achieved under fixed conversion ratios. Hybrid converters are thus emerged recently to combine the advantages of CB and SC converters. Converter topologies such as flying-capacitor multi-level (FCML) [1] and hybrid Dickson (HD) [2] adopt an external output LC filter after the SC network to realize continuous conversion range. However, since flying capacitor in [1] and [2] requires proper voltage balancing in the steady state, the switching frequency, $\\mathsf{f}_{\\mathsf{SW}}$, can be significantly slowed down when the converter needs to balance an increased number of the flying capacitor under small CR condition. Both double step-down (DSD) [3] and tri-state DSD [4] topologies can double $\\mathsf{f}_{\\mathsf{SW}}$ by using two inductors, but their CR is only $\\mathsf{D}/2$ that limits their capability to support 48V-to-1V conversions. Although the 12-level series-capacitor converter [5] topology significantly decreases the CR, it requires 11 flying capacitors and a $\\mathsf{GaN}$ FET as external components. The converter also has 24 on-chip power transistors to support 12-phase operation, resulting in a large chip area.","PeriodicalId":6830,"journal":{"name":"2022 IEEE International Solid- State Circuits Conference (ISSCC)","volume":"65 1","pages":"234-236"},"PeriodicalIF":0.0000,"publicationDate":"2022-02-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"7","resultStr":"{\"title\":\"A 2.5-5MHz 87% Peak Efficiency 48V-to-1V Integrated Hybrid DC-DC Converter Adopting Ladder SC Network with Capacitor-Assisted Dual-Inductor Filtering\",\"authors\":\"Chen Chen, Jin Liu, Hoi Lee\",\"doi\":\"10.1109/ISSCC42614.2022.9731764\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"With the rapid developments in big data analytics, non-isolated 48V-to-1V converters offer a competitive choice to support the increased power consumptions in CPUs and memories. For realizing a small output-to-input conversion ratio (CR), the conventional buck (CB) converters suffer from extremely short switch on-time that limits high-frequency operation and incurs high power losses. Although the switched-capacitor (SC) converters with lower voltage rating devices can scale down the high input voltage, $\\\\mathsf{V}_{\\\\mathsf{lN}}$, high efficiency can only be achieved under fixed conversion ratios. Hybrid converters are thus emerged recently to combine the advantages of CB and SC converters. Converter topologies such as flying-capacitor multi-level (FCML) [1] and hybrid Dickson (HD) [2] adopt an external output LC filter after the SC network to realize continuous conversion range. However, since flying capacitor in [1] and [2] requires proper voltage balancing in the steady state, the switching frequency, $\\\\mathsf{f}_{\\\\mathsf{SW}}$, can be significantly slowed down when the converter needs to balance an increased number of the flying capacitor under small CR condition. Both double step-down (DSD) [3] and tri-state DSD [4] topologies can double $\\\\mathsf{f}_{\\\\mathsf{SW}}$ by using two inductors, but their CR is only $\\\\mathsf{D}/2$ that limits their capability to support 48V-to-1V conversions. Although the 12-level series-capacitor converter [5] topology significantly decreases the CR, it requires 11 flying capacitors and a $\\\\mathsf{GaN}$ FET as external components. The converter also has 24 on-chip power transistors to support 12-phase operation, resulting in a large chip area.\",\"PeriodicalId\":6830,\"journal\":{\"name\":\"2022 IEEE International Solid- State Circuits Conference (ISSCC)\",\"volume\":\"65 1\",\"pages\":\"234-236\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2022-02-20\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"7\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2022 IEEE International Solid- State Circuits Conference (ISSCC)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ISSCC42614.2022.9731764\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2022 IEEE International Solid- State Circuits Conference (ISSCC)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ISSCC42614.2022.9731764","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A 2.5-5MHz 87% Peak Efficiency 48V-to-1V Integrated Hybrid DC-DC Converter Adopting Ladder SC Network with Capacitor-Assisted Dual-Inductor Filtering
With the rapid developments in big data analytics, non-isolated 48V-to-1V converters offer a competitive choice to support the increased power consumptions in CPUs and memories. For realizing a small output-to-input conversion ratio (CR), the conventional buck (CB) converters suffer from extremely short switch on-time that limits high-frequency operation and incurs high power losses. Although the switched-capacitor (SC) converters with lower voltage rating devices can scale down the high input voltage, $\mathsf{V}_{\mathsf{lN}}$, high efficiency can only be achieved under fixed conversion ratios. Hybrid converters are thus emerged recently to combine the advantages of CB and SC converters. Converter topologies such as flying-capacitor multi-level (FCML) [1] and hybrid Dickson (HD) [2] adopt an external output LC filter after the SC network to realize continuous conversion range. However, since flying capacitor in [1] and [2] requires proper voltage balancing in the steady state, the switching frequency, $\mathsf{f}_{\mathsf{SW}}$, can be significantly slowed down when the converter needs to balance an increased number of the flying capacitor under small CR condition. Both double step-down (DSD) [3] and tri-state DSD [4] topologies can double $\mathsf{f}_{\mathsf{SW}}$ by using two inductors, but their CR is only $\mathsf{D}/2$ that limits their capability to support 48V-to-1V conversions. Although the 12-level series-capacitor converter [5] topology significantly decreases the CR, it requires 11 flying capacitors and a $\mathsf{GaN}$ FET as external components. The converter also has 24 on-chip power transistors to support 12-phase operation, resulting in a large chip area.