一种带插入D >.5控制的4A 12对1飞电容交叉连接DC-DC变换器,实现了>倍的瞬态电感电流转换率和0.73倍的DSD理论最小输出欠冲

Tingxu Hu, Mo Huang, Yan Lu, R. Martins
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引用次数: 14

摘要

汽车和工业应用需要高效的DC-DC转换器,将功率从12V中间总线直接转换为低压负载点(PoL)。双降压(DSD)降压转换器[1]-[4](如图18.3.1所示)适用于这种应用,其中飞行电容器$C_{\mathrm{F}}$承受一半输入电压$(V_{\text{IN}}/2)$应力。因此,所有的电源开关只经历$V_{\text{IN}}/2$应力除了$M_{\mathrm{A}2}$,允许利用低压设备的好处。两个脉宽调制(PWM)信号$\phi_{1}$和$\phi_{2}$具有相等的占空比$D$驱动DSD。如果需要快速动态电压缩放(DVS),则$\text{PoL}$电源应具有小输出电容$C_{0}$。然而,在一个瞬态事件期间,传统DSD中的一个小$C_{0}$可能会导致一个大的输出欠冲$V_{\text{US}}$。这来自于低电感电流转换率$I_{\mathrm{L}_{-}\text{SR}}=(V_{\text{IN}}/2-2V_{0})/L$,由于电感开关节点$V_{\text{XA}1}$和$V_{\text{XB}1}$的振幅通过$C_{\mathrm{F}}$减少到$V_{\text{IN}}/2$,以及传统$D\leq 0.5$控制中的非重叠$\phi_{1}$和$\phi_{2}$。此外,$D$应覆盖广泛的范围,以响应控制回路补偿器中的积分瞬态误差。使用$D\leq 0.5$时,DSD转换器可能无法及时消除误差,误差的积累和释放导致超调/振铃。在较高的输出电压$V_{0}$下,这将更加严重,因为稳态$D$更接近0.5。一个可能的解决方案是使用$D>0.5$的DSD转换器。然而,这会导致$M_{\mathrm{A}1}$上的过度应力,以及电感电流$I_{\text{LA}}$和$I_{\text{LB}}$的不平衡,这应该被消除。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
A 4A 12-to-1 Flying Capacitor Cross-Connected DC-DC Converter with Inserted D>0.5 Control Achieving >2x Transient Inductor Current Slew Rate and 0.73× Theoretical Minimum Output Undershoot of DSD
Automotive and industrial applications require a high-efficiency DC-DC converter to directly convert power from the 12V intermediate bus to a low-voltage point-of-load (PoL). The double step-down (DSD) buck converter [1]–[4] (shown in Fig. 18.3.1) is suitable for such applications, where a flying capacitor $C_{\mathrm{F}}$ sustains a half-input-voltage $(V_{\text{IN}}/2)$ stress. Therefore, all the power switches only experience $V_{\text{IN}}/2$ stress except $M_{\mathrm{A}2}$, allowing for exploiting the benefits of low-voltage devices. Two pulse-width modulation (PWM) signals $\phi_{1}$ and $\phi_{2}$ with an equal duty cycle $D$ drive the DSD. A $\text{PoL}$ supply should have a small output capacitor $C_{0}$ if a fast dynamic voltage scaling (DVS) is needed. However, a small $C_{0}$ in the conventional DSD may cause a large output undershoot $V_{\text{US}}$ during a transient event. This comes from the low inductor current slew rate $I_{\mathrm{L}_{-}\text{SR}}=(V_{\text{IN}}/2-2V_{0})/L$, due to the amplitude of the inductor switching nodes $V_{\text{XA}1}$ and $V_{\text{XB}1}$ being reduced to $V_{\text{IN}}/2$ by $C_{\mathrm{F}}$, and the non-overlapping $\phi_{1}$ and $\phi_{2}$ in a conventional $D\leq 0.5$ control. Furthermore, the $D$ should cover a wide range to respond to an integral transient error in the control loop compensator. With $D\leq 0.5$, the DSD converter may fail to cancel the error in time, and the accumulation and release of the error result in overshoot/ringing. This would be more severe at a higher output voltage $V_{0}$ because the steady-state $D$ is closer to 0.5. A possible solution can be to have a DSD converter that works with $D>0.5$. Nevertheless, this leads to an over-sterss on $M_{\mathrm{A}1}$, and imbalance in inductor currents $I_{\text{LA}}$ and $I_{\text{LB}}$, which should be eliminated [3].
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