A. Peizerat, J. Rostaing, N. Zitouni, N. Baier, F. Guellec, R. Jalby, M. Tchagaspanian
{"title":"88dB信噪比,30µm像素间距红外图像传感器,具有2步16位a /D转换","authors":"A. Peizerat, J. Rostaing, N. Zitouni, N. Baier, F. Guellec, R. Jalby, M. Tchagaspanian","doi":"10.1109/VLSIC.2012.6243823","DOIUrl":null,"url":null,"abstract":"A new readout IC (ROIC) with a 2 step A/D conversion for cooled infrared image sensors is presented in this paper. The sensor operates at a 50Hz frame rate in an Integrate-While-Read snapshot mode. The 16 bit ADC resolution preserves the excellent detector SNR at full well (~3Ge-). The ROIC, featuring a 320×256 array with 30μm pixel pitch, has been designed in a standard 0.18μm CMOS technology. The IC has been hybridized (indium bump bonding) to a LWIR (Long Wave Infra Red) detector fabricated using our in-house HgCdTe process. The first measurement results of the detector assembly validate both the 2-step ADC concept and its circuit implementation. This work sets a new state-of-the-art SNR of 88dB.","PeriodicalId":6347,"journal":{"name":"2012 Symposium on VLSI Circuits (VLSIC)","volume":"1 1","pages":"128-129"},"PeriodicalIF":0.0000,"publicationDate":"2012-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"10","resultStr":"{\"title\":\"An 88dB SNR, 30µm pixel pitch Infra-Red image sensor with a 2-step 16 bit A/D conversion\",\"authors\":\"A. Peizerat, J. Rostaing, N. Zitouni, N. Baier, F. Guellec, R. Jalby, M. Tchagaspanian\",\"doi\":\"10.1109/VLSIC.2012.6243823\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A new readout IC (ROIC) with a 2 step A/D conversion for cooled infrared image sensors is presented in this paper. The sensor operates at a 50Hz frame rate in an Integrate-While-Read snapshot mode. The 16 bit ADC resolution preserves the excellent detector SNR at full well (~3Ge-). The ROIC, featuring a 320×256 array with 30μm pixel pitch, has been designed in a standard 0.18μm CMOS technology. The IC has been hybridized (indium bump bonding) to a LWIR (Long Wave Infra Red) detector fabricated using our in-house HgCdTe process. The first measurement results of the detector assembly validate both the 2-step ADC concept and its circuit implementation. This work sets a new state-of-the-art SNR of 88dB.\",\"PeriodicalId\":6347,\"journal\":{\"name\":\"2012 Symposium on VLSI Circuits (VLSIC)\",\"volume\":\"1 1\",\"pages\":\"128-129\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2012-06-13\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"10\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2012 Symposium on VLSI Circuits (VLSIC)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/VLSIC.2012.6243823\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2012 Symposium on VLSI Circuits (VLSIC)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/VLSIC.2012.6243823","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
An 88dB SNR, 30µm pixel pitch Infra-Red image sensor with a 2-step 16 bit A/D conversion
A new readout IC (ROIC) with a 2 step A/D conversion for cooled infrared image sensors is presented in this paper. The sensor operates at a 50Hz frame rate in an Integrate-While-Read snapshot mode. The 16 bit ADC resolution preserves the excellent detector SNR at full well (~3Ge-). The ROIC, featuring a 320×256 array with 30μm pixel pitch, has been designed in a standard 0.18μm CMOS technology. The IC has been hybridized (indium bump bonding) to a LWIR (Long Wave Infra Red) detector fabricated using our in-house HgCdTe process. The first measurement results of the detector assembly validate both the 2-step ADC concept and its circuit implementation. This work sets a new state-of-the-art SNR of 88dB.