采用频率型斩波稳定方案的20位25khz δ σ A/D转换器

Proceedings of the IEEE 2000 Custom Integrated Circuits Conference (Cat. No.00CH37044) Pub Date : 2000-05-24 DOI:10.1109/CICC.2000.852607

C. B. Wang

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引用次数: 50

摘要

一个20位δ σ A/D转换器实现在0.6 /spl mu/m CMOS工艺与单个5 V电源。它为高速直流测量提供25 kHz数据速率，同时保持精确直流测量所需的良好性能，如噪声，线性度和漂移。前端可编程增益放大器允许用户优化他们的系统与不同范围的输入电平。在PGA部分采用了偏置和有限增益补偿技术，以减小偏置，提高放大器的线性性能。在δ σ变换器部分，通过斩波稳定技术实现了低频误差的减小。采用了一种新型的频率型斩波稳定方案来缓解由于δ σ调制器使用固定频率斩波而产生的互调音。该A/D转换器在增益为1的情况下实现2.8 ppm的RMS噪声和12 ppm的INL。

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A 20 bit 25 kHz delta sigma A/D converter utilizing frequency-shaped chopper stabilization scheme

A 20 bit delta sigma A/D converter is implemented in a 0.6 /spl mu/m CMOS process with a single 5 V supply. It provides a 25 kHz data rate for high speed DC measurement while maintaining good performance required by accurate DC measurement such as noise, linearity and drift. The front-end programmable gain amplifier allows the users to optimize their system with different ranges of input level. Offset and finite gain compensation technique is used in the PGA section to reduce offset and improve linearity performance of the amplifier. In the delta sigma converter section, low frequency error reduction is achieved through chopper stabilization technique. A novel frequency-shaped chopper stabilization scheme is used to alleviate the inter-modulation tone which commonly exists due to the use of fix frequency chopping in delta sigma modulators. This A/D converter achieves 2.8 ppm RMS noise and 12 ppm INL at a gain of one.

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Proceedings of the IEEE 2000 Custom Integrated Circuits Conference (Cat. No.00CH37044)

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