T. Shimpi, Carey Reich, A. Danielson, A. Munshi, Anna Kindvall, Ramesh Pandey, K. Barth, W. Sampath
{"title":"工艺参数和吸收层厚度对多晶CdSeTe/CdTe薄膜太阳能电池效率的影响","authors":"T. Shimpi, Carey Reich, A. Danielson, A. Munshi, Anna Kindvall, Ramesh Pandey, K. Barth, W. Sampath","doi":"10.1109/PVSC45281.2020.9300840","DOIUrl":null,"url":null,"abstract":"Graded absorbers devices with with CdSe0.4Te0.6 (molar basis) and CdTe were fabricated. CdCl2 treatment time, post-deposition CdCl2 anneal time and thicknesses of CdSeTe and CdTe layers were varied. Photoluminescence and electrical measurements were performed on the fabricated devices. Results revealed that the individual thicknesses of CdSeTe and CdTe is critical to overall efficiency of the devices. Device fabricated on substrate with 0.5 µm CdSeTe, 3 µm CdTe with rest of process parameters kept unchanged, produced an efficiency of 20.14%. We report highest device efficiency among academia and research institutions.","PeriodicalId":6773,"journal":{"name":"2020 47th IEEE Photovoltaic Specialists Conference (PVSC)","volume":"7 1","pages":"1933-1935"},"PeriodicalIF":0.0000,"publicationDate":"2020-06-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"2","resultStr":"{\"title\":\"Influence of Process Parameters and Absorber Thickness on Efficiency of Polycrystalline CdSeTe/CdTe Thin Film Solar Cells\",\"authors\":\"T. Shimpi, Carey Reich, A. Danielson, A. Munshi, Anna Kindvall, Ramesh Pandey, K. Barth, W. Sampath\",\"doi\":\"10.1109/PVSC45281.2020.9300840\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Graded absorbers devices with with CdSe0.4Te0.6 (molar basis) and CdTe were fabricated. CdCl2 treatment time, post-deposition CdCl2 anneal time and thicknesses of CdSeTe and CdTe layers were varied. Photoluminescence and electrical measurements were performed on the fabricated devices. Results revealed that the individual thicknesses of CdSeTe and CdTe is critical to overall efficiency of the devices. Device fabricated on substrate with 0.5 µm CdSeTe, 3 µm CdTe with rest of process parameters kept unchanged, produced an efficiency of 20.14%. We report highest device efficiency among academia and research institutions.\",\"PeriodicalId\":6773,\"journal\":{\"name\":\"2020 47th IEEE Photovoltaic Specialists Conference (PVSC)\",\"volume\":\"7 1\",\"pages\":\"1933-1935\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2020-06-14\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"2\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2020 47th IEEE Photovoltaic Specialists Conference (PVSC)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/PVSC45281.2020.9300840\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2020 47th IEEE Photovoltaic Specialists Conference (PVSC)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/PVSC45281.2020.9300840","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Influence of Process Parameters and Absorber Thickness on Efficiency of Polycrystalline CdSeTe/CdTe Thin Film Solar Cells
Graded absorbers devices with with CdSe0.4Te0.6 (molar basis) and CdTe were fabricated. CdCl2 treatment time, post-deposition CdCl2 anneal time and thicknesses of CdSeTe and CdTe layers were varied. Photoluminescence and electrical measurements were performed on the fabricated devices. Results revealed that the individual thicknesses of CdSeTe and CdTe is critical to overall efficiency of the devices. Device fabricated on substrate with 0.5 µm CdSeTe, 3 µm CdTe with rest of process parameters kept unchanged, produced an efficiency of 20.14%. We report highest device efficiency among academia and research institutions.
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