{"title":"包围沟道无结场效应晶体管耗尽宽度模型","authors":"N. Das, Kaushik Chandra Deva Sarma","doi":"10.1109/ComPE49325.2020.9200004","DOIUrl":null,"url":null,"abstract":"A theoretical process of obtaining depletion width for surrounded channel Junction less field effect transistor is presented. Solution of 1-D Poisson’s equation under partial depletion leads to development of depletion width model. An analysis on how depletion width values varies with applied gate field, gate dielectric thickness, gate dielectric materials and channel position is also performed.","PeriodicalId":6804,"journal":{"name":"2020 International Conference on Computational Performance Evaluation (ComPE)","volume":"11 1","pages":"611-614"},"PeriodicalIF":0.0000,"publicationDate":"2020-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"Depletion Width Modelling of Surrounded Channel Junctionless Field Effect Transistor\",\"authors\":\"N. Das, Kaushik Chandra Deva Sarma\",\"doi\":\"10.1109/ComPE49325.2020.9200004\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A theoretical process of obtaining depletion width for surrounded channel Junction less field effect transistor is presented. Solution of 1-D Poisson’s equation under partial depletion leads to development of depletion width model. An analysis on how depletion width values varies with applied gate field, gate dielectric thickness, gate dielectric materials and channel position is also performed.\",\"PeriodicalId\":6804,\"journal\":{\"name\":\"2020 International Conference on Computational Performance Evaluation (ComPE)\",\"volume\":\"11 1\",\"pages\":\"611-614\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2020-07-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2020 International Conference on Computational Performance Evaluation (ComPE)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ComPE49325.2020.9200004\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2020 International Conference on Computational Performance Evaluation (ComPE)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ComPE49325.2020.9200004","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Depletion Width Modelling of Surrounded Channel Junctionless Field Effect Transistor
A theoretical process of obtaining depletion width for surrounded channel Junction less field effect transistor is presented. Solution of 1-D Poisson’s equation under partial depletion leads to development of depletion width model. An analysis on how depletion width values varies with applied gate field, gate dielectric thickness, gate dielectric materials and channel position is also performed.
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