Nishtha Wadhwa, J. Martins, P. Bahubalindruni, Sujay Deb, P. Barquinha
{"title":"柔性电子系统用A - igzo TFTs片上时钟发生器的比较研究","authors":"Nishtha Wadhwa, J. Martins, P. Bahubalindruni, Sujay Deb, P. Barquinha","doi":"10.1109/IFETC.2018.8583926","DOIUrl":null,"url":null,"abstract":"This paper presents a comparitive study of ring oscillators (RO) using amorphous Indium Gallium Zinc Oxide (a-IGZO) thin-film transistors (TFTs) to implement on-chip clock generator for flexible electronic systems. A five-stage RO has been implemented with different inverter topologies using IGZO TFTs, which includes Diode connected load, Capacitive bootstrapping (BS), Pseudo-CMOS and Pseudo-CMOS bootstrapping architectures. These topologies have been simulated using in-house IGZO TFT models under similar conditions using different power supplies (10 V, 15 V and 20 V) in cadence environment. Among all architechtures Capacitive bootstrapping RO has ensured highest frequency of operation in the order of MHz and an output swing of 82% of VDD. Whereas, Pseudo-CMOS based RO provides the lowest power consumption in the order of μW with an output swing of 57% of VDD. On the other hand, the combination of Pseudo CMOS and bootstrapping has ensured highest voltage swing of 95% of VDD. In terms of power delay product (PDP) BS RO is superior with respect to other topologies. This work provides a clear insight to the designer to choose a particular topology for given application, mainly for on-chip clock generation for flexible electronic systems based on the requirements.","PeriodicalId":6609,"journal":{"name":"2018 International Flexible Electronics Technology Conference (IFETC)","volume":"17 1","pages":"1-6"},"PeriodicalIF":0.0000,"publicationDate":"2018-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"3","resultStr":"{\"title\":\"A Comparitive Study of On-Chip Clock Generators Using a-IGZO TFTs for Flexible Electronic Systems\",\"authors\":\"Nishtha Wadhwa, J. Martins, P. Bahubalindruni, Sujay Deb, P. Barquinha\",\"doi\":\"10.1109/IFETC.2018.8583926\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This paper presents a comparitive study of ring oscillators (RO) using amorphous Indium Gallium Zinc Oxide (a-IGZO) thin-film transistors (TFTs) to implement on-chip clock generator for flexible electronic systems. A five-stage RO has been implemented with different inverter topologies using IGZO TFTs, which includes Diode connected load, Capacitive bootstrapping (BS), Pseudo-CMOS and Pseudo-CMOS bootstrapping architectures. These topologies have been simulated using in-house IGZO TFT models under similar conditions using different power supplies (10 V, 15 V and 20 V) in cadence environment. Among all architechtures Capacitive bootstrapping RO has ensured highest frequency of operation in the order of MHz and an output swing of 82% of VDD. Whereas, Pseudo-CMOS based RO provides the lowest power consumption in the order of μW with an output swing of 57% of VDD. On the other hand, the combination of Pseudo CMOS and bootstrapping has ensured highest voltage swing of 95% of VDD. In terms of power delay product (PDP) BS RO is superior with respect to other topologies. This work provides a clear insight to the designer to choose a particular topology for given application, mainly for on-chip clock generation for flexible electronic systems based on the requirements.\",\"PeriodicalId\":6609,\"journal\":{\"name\":\"2018 International Flexible Electronics Technology Conference (IFETC)\",\"volume\":\"17 1\",\"pages\":\"1-6\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2018-08-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"3\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2018 International Flexible Electronics Technology Conference (IFETC)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/IFETC.2018.8583926\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2018 International Flexible Electronics Technology Conference (IFETC)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/IFETC.2018.8583926","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A Comparitive Study of On-Chip Clock Generators Using a-IGZO TFTs for Flexible Electronic Systems
This paper presents a comparitive study of ring oscillators (RO) using amorphous Indium Gallium Zinc Oxide (a-IGZO) thin-film transistors (TFTs) to implement on-chip clock generator for flexible electronic systems. A five-stage RO has been implemented with different inverter topologies using IGZO TFTs, which includes Diode connected load, Capacitive bootstrapping (BS), Pseudo-CMOS and Pseudo-CMOS bootstrapping architectures. These topologies have been simulated using in-house IGZO TFT models under similar conditions using different power supplies (10 V, 15 V and 20 V) in cadence environment. Among all architechtures Capacitive bootstrapping RO has ensured highest frequency of operation in the order of MHz and an output swing of 82% of VDD. Whereas, Pseudo-CMOS based RO provides the lowest power consumption in the order of μW with an output swing of 57% of VDD. On the other hand, the combination of Pseudo CMOS and bootstrapping has ensured highest voltage swing of 95% of VDD. In terms of power delay product (PDP) BS RO is superior with respect to other topologies. This work provides a clear insight to the designer to choose a particular topology for given application, mainly for on-chip clock generation for flexible electronic systems based on the requirements.