衬底取向和蚀刻条件对硅纳米线形成的影响

2010 International Conference on Enabling Science and Nanotechnology (ESciNano) Pub Date : 2010-12-01 DOI:10.1109/ESCINANO.2010.5700956

Tan Lay Theng, H. Hui, C. Sheng, O. Soon, M. T. Sun, Wee Qixun, Soh Chew Beng, Chua Soo Jin

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引用次数: 1

摘要

硅纳米线(SiNWs)由于其优异的电学、力学和光学特性以及潜在的应用，从纳米/微机电系统到光电子学和生物/化学传感器都受到了极大的关注[1-2]。化学刻蚀法是直接从块状硅片合成硅纳米线阵列的常用方法之一。然而，这种方法面临的困难是如何很好地控制纳米线的分布和尺寸。

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Dependence of substrate orientation and etching conditions on the formation of Si nanowires

Silicon nanowires (SiNWs) have received great interest because of their excellent electrical, mechanical, and optical properties as well as their potential applications, ranging from nano/micro-electromechanical system to optoelectronics, and biological/chemical sensors [1–2]. One of the common methods to synthesize Si nanowire arrays directly from bulk silicon wafers is through electroless etching. However the difficulties faced in this method are achieving good control over the distribution and size of the nanowires.

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2010 International Conference on Enabling Science and Nanotechnology (ESciNano)

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