一种基于单晶振荡器的时钟管理IC,具有18倍启动时间缩短和0.68ppm/ºC占空比机器学习的RCO校准

Jaehong Jung, Seunghyun Oh, Joo-Myoung Kim, Gihyeok Ha, Jinhyeon Lee, Seungjin Kim, Euiyoung Park, Jaehoon Lee, Yelim Yoon, Seung-Jun Bae, Won-Woong Kim, Yong Lim, Kyungsoo Lee, Junho Huh, Jongwoo Lee, T. B. Cho
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引用次数: 9

摘要

传统的蜂窝移动设备需要一个数十mhz的主晶振(XO)和32.768kHz的实时时钟(RTC) XO,分别用于射频超低抖动锁相环和睡眠工作。为了通过减少晶体数量来最小化BoM成本和PCB面积,在RTC中报告了[1]中带有分数分频器(DIV)的低功耗主XO。然而,高q因子主XO的高功耗启动操作是不可避免的。片上RC振荡器(RCO)可以替代RTC XO,因为它面积小,在过程、电压和温度(PVT)变化上具有出色的稳定性。为了提高RCO的温度灵敏度,在[2]中采用了使用具有相反温度系数(TC)的电阻的两点微调,但由于$1^{\text{st}}$阶补偿,精度限制在20ppm/ºC。[3]、[4]中使用高分辨率温度传感器单元(tsu)的rco可以将TC提高到<10ppm/ºC。然而,TSU需要很大的面积和外部FPGA来处理复杂的数字信号。此外,先前的[2]-[4]方法只能应用于提供负TC电阻的有限过程。主XO应该实现射频锁相环的超低抖动(即$< 100{\text{fs}}_{\text{rms}})$,但由于XO的大摆幅导致启动时间长。因此,系统待机功率增加。虽然[5]中精确定时的能量注入可以有效减少启动时间,但只适用于时钟摆动较小(0.32V)的情况。采用两步注入技术[6],即使摆幅较大,XO的启动时间也能提高到接近理论极限,但锁相环参考时钟缓冲器的短路电流限制了启动能量的降低(3.4倍)。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
A Single-Crystal-Oscillator-Based Clock-Management IC with 18× Start-Up Time Reduction and 0.68ppm/ºC Duty-Cycled Machine-Learning-Based RCO Calibration
The conventional cellular mobile device needs a tens-of-MHz main crystal oscillator (XO) and 32.768kHz real-time clock (RTC) XO for RF ultra-low-jitter PLLs and sleep operation, respectively. To minimize BoM cost and PCB area by reducing the number of crystals, the low-power main XO with a fractional divider (DIV.) in [1] is reported for the RTC. However, the high-power-consuming start-up operation for high-Q-factor main XO is inevitable. The on-chip RC oscillator (RCO) can be an alternative to the RTC XO due to its compact area and excellent stability over process, voltage, and temperature (PVT) variation. To improve the temperature sensitivity of the RCO, the two-point trimming using the resistors having the opposite temperature coefficient (TC) is employed in [2], but the accuracy is limited to 20ppm/ºC due to the $1^{\text{st}}$ -order compensation. The RCOs using high-resolution temperature-sensor units (TSUs) in [3], [4] can improve the TC up to <10ppm/ºC. However, the TSU requires a large area and an external FPGA to address complex digital signals. In addition, the previous approaches of [2]–[4] can be applied only to the limited processes providing a negative TC resistor. The main XO should accomplish ultra-low jitter for the RF PLLs (i.e $< 100{\text{fs}}_{\text{rms}})$, but it causes long start-up time due to a large swing of the XO. Consequently, the system stand-by power is increased. Although a precisely timed energy injection in [5] can effectively reduce the start-up time, it is only applicable when the clock swing is small (0.32V). The 2-step injection technique [6] can improve the start-up time of the XO close to the theoretical limit even with large swing, but the short-circuit current of the buffer for a reference clock of the PLL restricts the start-up energy reduction (3.4×).
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