Power supply noise suppression via clock skew scheduling

Simultaneous switching events in the clock lines and the signals passing through sequential and combinational logic elements cause large L/spl middot/di/dt and IR voltage variations in the power and ground network. This is known as power supply noise and it affects the performance and reliability of the entire circuit. In this paper, we propose an algorithm that performs clock skew scheduling to minimize the number of simultaneous switching events such that the power supply noise is suppressed. Our approach establishes a direct relationship between current (drawn by a circuit element, sequential or combinational) and skew by the concept of envelope waveforms, using a graphical representation. We provide a graph-based scheduling approach to reduce the peak current and to minimize the difference between the current peaks and valleys such that the current profile of the entire circuit is smoothened. Our approach also guarantees that the resulting clock schedule does not violate setup and hold time constraints. Experimental results on benchmark circuits show an average reduction of 19.6% in the peak current, an average reduction of 38.7% in the current swing, and an average reduction of 47.4% in voltage variations in the power lines.