使用系统场景创建处理器性能可变性的运行时松弛

Michail Noltsis, D. Rodopoulos, N. Zompakis, F. Catthoor, D. Soudris
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引用次数: 3

摘要

现代微处理器包含各种用于减轻逻辑和内存错误的机制,称为可靠性、可用性和可服务性(RAS)技术。这些技术中的许多,比如组件禁用,都是以性能为代价的。随着设备尺寸的大幅缩小,可以合理地预期,芯片范围内的错误率将在未来加剧,并可能在整个系统生命周期中发生变化。因此,以系统的方式回收临时RAS开销并启用可靠的性能非常重要。本文提出了一种基于检测到的时序干扰来驱动处理器频率的闭环控制方案,以保证性能的可靠性。为了支持离散时间控制问题的表述,引入了松弛和最后期限脆弱性因子的概念。使用系统场景方法推导缺省应用程序定时,通过模拟演示了该方法的适用性。此外,提出的概念在一个真实的平台和应用程序中得到了演示:在应用程序中实现的比例-积分-微分控制器驱动Linux内核的动态电压和频率缩放(DVFS)框架,以有效地回收在运行时注入的时间开销。本文讨论了所提出的性能可靠性方案的响应性和能效。最后,引入了额外的公式来预测可以通过驱动任何处理器的DVFS吸收的时序干扰的上界,并在具有代表性的简化到实践中进行了验证。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
Runtime Slack Creation for Processor Performance Variability using System Scenarios
Modern microprocessors contain a variety of mechanisms used to mitigate errors in the logic and memory, referred to as Reliability, Availability, and Serviceability (RAS) techniques. Many of these techniques, such as component disabling, come at a performance cost. With the aggressive downscaling of device dimensions, it is reasonable to expect that chip-wide error rates will intensify in the future and perhaps vary throughout system lifetime. As a result, it is important to reclaim the temporal RAS overheads in a systematic way and enable dependable performance. The current article presents a closed-loop control scheme that actuates processor’s frequency based on detected timing interference to ensure performance dependability. The concepts of slack and deadline vulnerability factor are introduced to support the formulation of a discrete time control problem. Default application timing is derived using the system scenario methodology, the applicability of which is demonstrated through simulations. Additionally, the proposed concept is demonstrated on a real platform and application: a Proportional-Integral-Differential controller, implemented within the application, actuates the Dynamic Voltage and Frequency Scaling (DVFS) framework of the Linux kernel to effectively reclaim temporal overheads injected at runtime. The current article discusses the responsiveness and energy efficiency of the proposed performance dependability scheme. Finally, additional formulation is introduced to predict the upper bound of timing interference that can be absorbed by actuating the DVFS of any processor and is also validated on a representative reduction to practice.
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