STREX:通过分层事务执行提高OLTP工作负载中的指令缓存重用

Islam Atta, Pınar Tözün, Xin Tong, A. Ailamaki, Andreas Moshovos
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引用次数: 23

摘要

联机事务处理(OLTP)工作负载性能受到指令停滞的影响;典型事务的指令占用远远超过L1缓存的容量,从而导致持续的缓存抖动。几种建议的技术移除了一些指令停顿,以换取对代码库进行容易出错的插装,或者大幅度增加L1-I缓存单元的面积和功率。另一些则通过更好地利用共享L2缓存来减少指令遗漏延迟。SLICC[2]是最近提出的一种利用事务指令局域性的线程迁移技术,它有望用于高核数,但在少数核上运行时性能不佳或可能会损害性能。本文证实了OLTP事务在其指令占用中表现出显著的线程内和线程间重叠,并分析了指令延迟减少的好处。本文介绍了STREX,一种硬件、程序员透明的技术,它利用典型的事务行为来提高一级缓存中的指令重用。STREX在单个核心上动态地执行类似的事务,以便一个事务获取的指令尽可能地被系统中执行的所有其他事务重用。STREX通过观察块何时被带入缓存以及何时被驱逐,将每个事务的执行动态地划分为缓存大小的段。实验表明,与2- 16核的基准执行相比,STREX持续提高性能,同时将L1指令和数据丢失的数量平均分别减少37%和14%。最后,本文提出了一种实用的混合技术,它结合了STREX和SLICC,从而保证了性能优势,而不管可用内核的数量和工作负载的占用。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
STREX: boosting instruction cache reuse in OLTP workloads through stratified transaction execution
Online transaction processing (OLTP) workload performance suffers from instruction stalls; the instruction footprint of a typical transaction exceeds by far the capacity of an L1 cache, leading to ongoing cache thrashing. Several proposed techniques remove some instruction stalls in exchange for error-prone instrumentation to the code base, or a sharp increase in the L1-I cache unit area and power. Others reduce instruction miss latency by better utilizing a shared L2 cache. SLICC [2], a recently proposed thread migration technique that exploits transaction instruction locality, is promising for high core counts but performs sub-optimally or may hurt performance when running on few cores. This paper corroborates that OLTP transactions exhibit significant intra- and inter-thread overlap in their instruction footprint, and analyzes the instruction stall reduction benefits. This paper presents STREX, a hardware, programmer-transparent technique that exploits typical transaction behavior to improve instruction reuse in first level caches. STREX time-multiplexes the execution of similar transactions dynamically on a single core so that instructions fetched by one transaction are reused by all other transactions executing in the system as much as possible. STREX dynamically slices the execution of each transaction into cache-sized segments simply by observing when blocks are brought in the cache and when they are evicted. Experiments show that, when compared to baseline execution on 2--16 cores, STREX consistently improves performance while reducing the number of L1 instruction and data misses by 37% and 14% on average, respectively. Finally, this paper proposes a practical hybrid technique that combines STREX and SLICC, thereby guaranteeing performance benefits regardless of the number of available cores and the workload's footprint.
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