{"title":"电流模式算法流水线模数转换器","authors":"A.J. Correia, J. Guilherme, J. Franca","doi":"10.1109/APCAS.1996.569300","DOIUrl":null,"url":null,"abstract":"Current-mode integrated circuit design techniques offering full compatibility with mainstream digital CMOS technology have been investigated for the realization of an 8-bit 1 MHz analog-to-digital converter. This is based on a modular 1-bit-per-stage pipeline architecture employing a compact algorithmic processing circuitry in each stage. The prototype chip fabricated in a 1.2 /spl mu/m digital CMOS technology occupies 0.655 mm/sup 2/ of silicon area and dissipates 50 mW at 5 V supply.","PeriodicalId":20507,"journal":{"name":"Proceedings of APCCAS'96 - Asia Pacific Conference on Circuits and Systems","volume":null,"pages":null},"PeriodicalIF":0.0000,"publicationDate":"1996-11-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":"{\"title\":\"Current-mode algorithmic pipeline analog-to-digital converter\",\"authors\":\"A.J. Correia, J. Guilherme, J. Franca\",\"doi\":\"10.1109/APCAS.1996.569300\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Current-mode integrated circuit design techniques offering full compatibility with mainstream digital CMOS technology have been investigated for the realization of an 8-bit 1 MHz analog-to-digital converter. This is based on a modular 1-bit-per-stage pipeline architecture employing a compact algorithmic processing circuitry in each stage. The prototype chip fabricated in a 1.2 /spl mu/m digital CMOS technology occupies 0.655 mm/sup 2/ of silicon area and dissipates 50 mW at 5 V supply.\",\"PeriodicalId\":20507,\"journal\":{\"name\":\"Proceedings of APCCAS'96 - Asia Pacific Conference on Circuits and Systems\",\"volume\":null,\"pages\":null},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1996-11-18\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"1\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Proceedings of APCCAS'96 - Asia Pacific Conference on Circuits and Systems\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/APCAS.1996.569300\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings of APCCAS'96 - Asia Pacific Conference on Circuits and Systems","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/APCAS.1996.569300","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Current-mode integrated circuit design techniques offering full compatibility with mainstream digital CMOS technology have been investigated for the realization of an 8-bit 1 MHz analog-to-digital converter. This is based on a modular 1-bit-per-stage pipeline architecture employing a compact algorithmic processing circuitry in each stage. The prototype chip fabricated in a 1.2 /spl mu/m digital CMOS technology occupies 0.655 mm/sup 2/ of silicon area and dissipates 50 mW at 5 V supply.
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