一种0.4 V 6.4 μW 3.3 MHz CMOS自举弛豫振荡器,频率偏差±0.71%,范围为- 30至100°C,适用于可穿戴和传感应用

Ka-Meng Lei, Pui-in Mak, R. Martins
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引用次数: 2

摘要

可穿戴和传感电子设备正朝着从环境中收集能量(例如热能和太阳能)的方向发展。超低电压(ULV)电路允许通过低于0.5 V的能量源直接供电,可以最大限度地提高功率效率。这项工作是一个0.4 V 65 nm CMOS弛缓振荡器,具有自举逻辑门和输出。自举逻辑门使输出摆幅为1.15 V,克服了无额外电压源的超低电压数字电路的不利影响。具有批量驱动输入的ULV比较器具有3级联级,增益为18db。此外,内置校准的3.3 MHz弛豫振荡器具有背景延迟时间抵消方案,与蒙特卡罗模拟(N=30)相比,对温度(- 30至100°C)和电压(0.36至0.44 V)变化的频率偏差分别为±0.71%和±0.57%。模拟功耗为6.4 μW,每周期的能效为1.9 pJ。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
A 0.4 V 6.4 μW 3.3 MHz CMOS Bootstrapped Relaxation Oscillator with ±0.71% Frequency Deviation over −30 to 100 °C for Wearable and Sensing Applications
Wearable and sensing electronics are evolving towards energy harvesting from the environment (e.g. thermal and solar energy). Ultra-low-voltage (ULV) circuits that allow direct-powering by sub-0.5 V energy sources can maximize the power efficiency. This work is a 0.4 V 65 nm CMOS relaxation oscillator with bootstrapped logic gates and outputs. The bootstrapped logic gates enable an output swing of 1.15 V surmounting the adverse effect of ULV digital circuits without extra voltage source. The ULV comparator with bulk-driven-inputs shows an 18 dB gain with 3 cascaded stages. Also, featuring a background delay-time cancellation scheme, the 3.3 MHz relaxation oscillator with built-in calibration exhibits a frequency deviation of ±0.71% and ±0.57% against temperature (−30 to 100 °C) and voltage (0.36 to 0.44 V) variations, respectively, from Monte-Carlo simulations (N=30). The simulated power consumption is 6.4 μW, resulting in an energy efficiency of 1.9 pJ per cycle.
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