多核功能缓存模拟器

2012 9th International Conference on Electrical Engineering/Electronics, Computer, Telecommunications and Information Technology Pub Date : 2012-05-16 DOI:10.1109/ECTICON.2012.6254278

P. Ratanaworabhan

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引用次数: 2

摘要

本文介绍了一种用于多核CPU的轻量级执行驱动缓存模拟器的设计和构造。我们将模拟器作为Pin工具来实现，运行在Intel开发的动态仪器工具Pin之上。然后，我们使用它来研究从两个公认的基准套件SPLASH2和PARSEC中选择的13个多线程程序的缓存行为。我们计划将该工具作为开源软件发布，并希望计算机体系结构研究社区能够从中受益。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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Functional cache simulator for multicore

This paper presents the design and construction of a light-weight execution-driven cache simulator for multicore CPU. We implement the simulator as a Pin tool, running on top of Pin, a dynamic instrumentation tool developed by Intel. We then use it to study the cache behavior of 13 multithreaded programs selected from the two well-recognized benchmark suites, SPLASH2 and PARSEC. We plan to release the tool as open-source software and hope that the computer architecture research community would benefit from it.

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来源期刊

2012 9th International Conference on Electrical Engineering/Electronics, Computer, Telecommunications and Information Technology

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