An efficient built-in self-test algorithm for neighborhood pattern sensitive faults in high-density memories

As the density of memories increases, unwanted interference between cells is increased and testing high density memories for a high degree of fault coverage can require either a relatively large number of test vectors or a significant amount of additional test circuitry. In this paper, a new thing method and an efficient BIST algorithm for NPSFs are proposed. Instead of the conventional five-cell and nine-cell physical neighborhood layouts to test memory cells, a four-cell layout is used. This four-cell layout requires smaller test vectors and shorter test time. A CMOS column decoder and the parallel comparator proposed by P. Mazumder and J.H. Patel are modified to implement test procedure which is appropriate for the four-cell layout. Consequently, these reduce the number of transistors used for a BIST circuit. Also, we present properties of the algorithm, such as its capability to detect stuck-at faults, transition faults, and conventional pattern sensitive faults.