用于22 ~ 31.4 GS/s实时采样系统的校准正交时钟发生器

Shunli Ma, Guangyao Zhou, Jia-Feng Jiang, Chixiao Chen, Yongzhen Chen, Fan Ye, Junyan Ren
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引用次数: 1

摘要

提出了一种用于超高速实时采样系统的带相位标定的精确正交时钟信号。所提出的四相时钟发生器是一个锁相环(PLL),具有一种新颖的正交分频器,可以实现可调的正交相位来校准可变失配。所提出的正交时钟的工作频率可以在5.5GHz到7.85GHz之间进行调谐,可用于四通道时间交错采样器。实时采样系统实现28-31.2GS/s的采样率。芯片功耗为28mW,电源电压为1.2V,采用台积电65nm CMOS工艺。测量结果表明,校准相位可以覆盖±10°的I相与Q相失配。相位噪声为-115 dBc/Hz@1MHz,中心频率为6.85GHz,周期间时间RMS抖动为210fs。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
A quadrature clock generator with calibration for 22∼31.4 GS/s real-time sampling system
This paper presents an accurate quadrature clock signals with phase calibration for ultra-high speed real-time sampling system. The proposed four-phase clock generator is a phase locked loop (PLL) with a novel quadrature divider which can realize tunable quadrature phase to calibrate variable mismatches. The operating frequency of the proposed quadrature clock can be tuned from 5.5GHz to 7.85GHz which can be used in four-channel time-interleaved sampler. The real-time sampling system achieve 28-31.2GS/s sampling rate. The chip consumes 28mW power with 1.2V supply voltage in TSMC 65 nm CMOS process. The measurements show that the calibration phase can cover ±10°I phase and Q phase mismatch. The phase noise is -115 dBc/Hz@1MHz offset frequency at 6.85GHz center frequency and cycle-to-cycle time RMS jitter is 210fs.
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