基于约简的条件验证器构造

Dirk Beyer, Marie-Christine Jakobs, T. Lemberger, H. Wehrheim
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引用次数: 27

摘要

尽管最近取得了进展,软件验证仍然具有挑战性。为了解决困难的验证任务,我们需要利用的不仅仅是一个,而是几个使用不同技术的不同的验证器。为此,我们需要在验证者之间交换信息。条件模型检查被提出作为这个问题的解决方案:其思想是让第一个验证者输出一个描述它成功验证的状态空间的条件,并指示第二个验证者使用这个条件来验证尚未验证的状态空间。然而,大多数验证器不理解条件作为输入。在本文中,我们提出了一种由给定的传统验证器和减速器组成的条件验证器的现成结构的使用。减速机将待验证程序和条件作为输入,输出残差程序,残差程序的路径覆盖条件所描述的未验证状态空间。作为概念验证,我们设计并实现了一个特定的减速机,并从SV-COMP 2017上的三个最佳验证器中组成了三个条件模型检查器。我们定义了一组声明,并通过实验评估了它们的有效性。所有实验数据和结果可用于复制。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
Reducer-Based Construction of Conditional Verifiers
Despite recent advances, software verification remains challenging. To solve hard verification tasks, we need to leverage not just one but several different verifiers employing different technologies. To this end, we need to exchange information between verifiers. Conditional model checking was proposed as a solution to exactly this problem: The idea is to let the first verifier output a condition which describes the state space that it successfully verified and to instruct the second verifier to verify the yet unverified state space using this condition. However, most verifiers do not understand conditions as input. In this paper, we propose the usage of an off-the-shelf construction of a conditional verifier from a given traditional verifier and a reducer. The reducer takes as input the program to be verified and the condition, and outputs a residual program whose paths cover the unverified state space described by the condition. As a proof of concept, we designed and implemented one particular reducer and composed three conditional model checkers from the three best verifiers at SV-COMP 2017. We defined a set of claims and experimentally evaluated their validity. All experimental data and results are available for replication.
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