On-Wafer Drain Current Variability in GaN MIS-HEMT on 200-mm Silicon Substrates

In this study, a detailed on-wafer (or global) variability analysis of drain current characteristics of GaN MIS-HEMT devices grown on 200 mm silicon substrate is conducted. For the first time to our knowledge, the on-wafer variability sources in GaN technologies due to the manufacturing process are investigated by combining experimental data and analytical variability modeling. The key parameters which affect the variability are oxide the interface charge fluctuations, the mobility fluctuations, the gate oxide thickness and/or the gate area variations and the access resistance fluctuations in the contact as well as in the 2DEG regions (source and drain sides). Due the specificity of GaN MIS HEMT device engineering process, we show that their variability performances are not, for the time being, comparable to the state-of-the art silicon CMOS technologies, and this can be valuable for reliable improvement and optimization of GaN technology fabrication process. This study has been verified over a large range of channel gate lengths for three normally-off GaN MIS-HEMT wafers and having different gate process flows.