一种用于聚类分析的新型VLSI架构

Proceedings of APCCAS'96 - Asia Pacific Conference on Circuits and Systems Pub Date : 1996-11-18 DOI:10.1109/APCAS.1996.569319

Mao-Fu Lai, C. Hsieh

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引用次数: 2

摘要

本文提出了一种新的基于平方误差聚类算法的VLSI结构。所建议的体系结构减少了其他先前体系结构所需的大量处理元素(pe)。该系统仅使用相邻pe之间的本地通信，具有模块化、规范化和可扩展性。基于所提出的架构，可以以显著降低的电路复杂度实现高速聚类分析的VLSI实现。

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A novel VLSI architecture for clustering analysis

This paper presents a novel VLSI architecture for the squared-error clustering algorithm. The proposed architecture reduces the huge number of processing elements (PEs) required by the other previous architectures. The system uses only local communication between adjacent PEs, and it is modular, regular, and expandable. The VLSI implementation of high speed clustering analysis can be realized with significantly less circuit complexity based on the proposed architecture.

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Proceedings of APCCAS'96 - Asia Pacific Conference on Circuits and Systems

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