E. You, S. Choe, Chin-Man Kim, L. Varadadesikan, K. Aingaran, J. MacDonald
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Parasitic extraction for multimillion-transistor integrated circuits: methodology and design experience
This paper discusses accuracy issues in parasitic extraction for the design of multimillion-transistor integrated circuits. The methodology reported aims at reducing the gap between the parasitic values estimated during implementation and the results of post-layout extraction. The objective is to obtain progressively refined interconnect models in hierarchical design flows. This methodology was developed for the 800 MHz UltraSPARC-III microprocessor. Our experimental results demonstrate the profound impact of the extraction methodology on interconnect modeling as well as subsequent timing and noise analyses.