Comparative Validation of SRAM Cells Designed using 18nm FinFET for Memory Storing Applications

The limitation of CMOS to operate under 25nm is a major concern, which is viewed in this paper. Also, scaling issues like leakage current, lower carrier mobility, higher junction capacitance limits the transistor operation is discussed. At lower voltage values, CMOS productive decreases drastically, which reflects on the performance of the circuit to achieve its criteria’s. In the present-day scenario of electronic industry, the speed of the processor is increasing, the urge for speed cache memory is also increasing. In cache memory design, SRAM cell is mainly used, CMOS SRAM Cells are producing more delay and also limitations like mentioned above. Therefore, an alternative preferred choice for SRAM Cells is FinFET, which increases the speed of the Cell by avoiding limitations caused by the bulk CMOS. By considering the advantages of the FinFET, SRAM Cells are implemented in Cadence virtuoso using FinFET 18nm Spectre. In this paper, standard SRAM Cells like 7T, 8T, 9T, and 1oT are simulated and parameters like power, delay, power delay product (PDP), energy-delay product (EDP) are calculated and respective values are presented by varying the voltage (V). SRAM Cells behavior under different voltages is graphically represented. CMOS SRAM Cell values have been taken from previous works of SRAM. By comparing the parameters, a drastic increase in the speed of the FinFET SRAM Cells can be observed over CMOS SRAM Cells.