A. Greene, Huimei Zhou, R. Xie, Chanro Park, L. Economikos, V. Chan, K. Akarvardar, R. Bao, I. Seshadri, R. Conti, Miaomiao Wang, M. Sankarapandian, J. Demarest, Juntao Li, Liying Jiang, K. Zhao, R. Robison, T. Ando, N. Cave, A. Knorr, D. Gupta, S. Kanakasabapathy, D. Guo, B. Haran, V. Basker, H. Bu
{"title":"RMG中的栅极切割,以实现栅极扩展缩放和寄生电容减小","authors":"A. Greene, Huimei Zhou, R. Xie, Chanro Park, L. Economikos, V. Chan, K. Akarvardar, R. Bao, I. Seshadri, R. Conti, Miaomiao Wang, M. Sankarapandian, J. Demarest, Juntao Li, Liying Jiang, K. Zhao, R. Robison, T. Ando, N. Cave, A. Knorr, D. Gupta, S. Kanakasabapathy, D. Guo, B. Haran, V. Basker, H. Bu","doi":"10.23919/VLSIT.2019.8776493","DOIUrl":null,"url":null,"abstract":"In this paper, we present for the first time a “Gate-Cut-Last” integration scheme completed within the Replacement Metal Gate (RMG) module. This novel gate cut (CT) technique allows the scaling of gate extension length past the end fin which reduces parasitic capacitance, leakage and performance variation. In addition, we demonstrate that CT-in-RMG is a promising alternative integration process that can enable scaling for future logic technology nodes. Device, circuit and reliability results are shown to compare this novel CT-in-RMG process to the conventional gate cut method.","PeriodicalId":6752,"journal":{"name":"2019 Symposium on VLSI Technology","volume":"41 1","pages":"T144-T145"},"PeriodicalIF":0.0000,"publicationDate":"2019-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":"{\"title\":\"Gate-Cut-Last in RMG to Enable Gate Extension Scaling and Parasitic Capacitance Reduction\",\"authors\":\"A. Greene, Huimei Zhou, R. Xie, Chanro Park, L. Economikos, V. Chan, K. Akarvardar, R. Bao, I. Seshadri, R. Conti, Miaomiao Wang, M. Sankarapandian, J. Demarest, Juntao Li, Liying Jiang, K. Zhao, R. Robison, T. Ando, N. Cave, A. Knorr, D. Gupta, S. Kanakasabapathy, D. Guo, B. Haran, V. Basker, H. Bu\",\"doi\":\"10.23919/VLSIT.2019.8776493\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"In this paper, we present for the first time a “Gate-Cut-Last” integration scheme completed within the Replacement Metal Gate (RMG) module. This novel gate cut (CT) technique allows the scaling of gate extension length past the end fin which reduces parasitic capacitance, leakage and performance variation. In addition, we demonstrate that CT-in-RMG is a promising alternative integration process that can enable scaling for future logic technology nodes. Device, circuit and reliability results are shown to compare this novel CT-in-RMG process to the conventional gate cut method.\",\"PeriodicalId\":6752,\"journal\":{\"name\":\"2019 Symposium on VLSI Technology\",\"volume\":\"41 1\",\"pages\":\"T144-T145\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2019-06-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"1\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2019 Symposium on VLSI Technology\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.23919/VLSIT.2019.8776493\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2019 Symposium on VLSI Technology","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.23919/VLSIT.2019.8776493","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Gate-Cut-Last in RMG to Enable Gate Extension Scaling and Parasitic Capacitance Reduction
In this paper, we present for the first time a “Gate-Cut-Last” integration scheme completed within the Replacement Metal Gate (RMG) module. This novel gate cut (CT) technique allows the scaling of gate extension length past the end fin which reduces parasitic capacitance, leakage and performance variation. In addition, we demonstrate that CT-in-RMG is a promising alternative integration process that can enable scaling for future logic technology nodes. Device, circuit and reliability results are shown to compare this novel CT-in-RMG process to the conventional gate cut method.