RMG中的栅极切割,以实现栅极扩展缩放和寄生电容减小

A. Greene, Huimei Zhou, R. Xie, Chanro Park, L. Economikos, V. Chan, K. Akarvardar, R. Bao, I. Seshadri, R. Conti, Miaomiao Wang, M. Sankarapandian, J. Demarest, Juntao Li, Liying Jiang, K. Zhao, R. Robison, T. Ando, N. Cave, A. Knorr, D. Gupta, S. Kanakasabapathy, D. Guo, B. Haran, V. Basker, H. Bu
{"title":"RMG中的栅极切割,以实现栅极扩展缩放和寄生电容减小","authors":"A. Greene, Huimei Zhou, R. Xie, Chanro Park, L. Economikos, V. Chan, K. Akarvardar, R. Bao, I. Seshadri, R. Conti, Miaomiao Wang, M. Sankarapandian, J. Demarest, Juntao Li, Liying Jiang, K. Zhao, R. Robison, T. Ando, N. Cave, A. Knorr, D. Gupta, S. Kanakasabapathy, D. Guo, B. Haran, V. Basker, H. Bu","doi":"10.23919/VLSIT.2019.8776493","DOIUrl":null,"url":null,"abstract":"In this paper, we present for the first time a “Gate-Cut-Last” integration scheme completed within the Replacement Metal Gate (RMG) module. This novel gate cut (CT) technique allows the scaling of gate extension length past the end fin which reduces parasitic capacitance, leakage and performance variation. In addition, we demonstrate that CT-in-RMG is a promising alternative integration process that can enable scaling for future logic technology nodes. Device, circuit and reliability results are shown to compare this novel CT-in-RMG process to the conventional gate cut method.","PeriodicalId":6752,"journal":{"name":"2019 Symposium on VLSI Technology","volume":"41 1","pages":"T144-T145"},"PeriodicalIF":0.0000,"publicationDate":"2019-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":"{\"title\":\"Gate-Cut-Last in RMG to Enable Gate Extension Scaling and Parasitic Capacitance Reduction\",\"authors\":\"A. Greene, Huimei Zhou, R. Xie, Chanro Park, L. Economikos, V. Chan, K. Akarvardar, R. Bao, I. Seshadri, R. Conti, Miaomiao Wang, M. Sankarapandian, J. Demarest, Juntao Li, Liying Jiang, K. Zhao, R. Robison, T. Ando, N. Cave, A. Knorr, D. Gupta, S. Kanakasabapathy, D. Guo, B. Haran, V. Basker, H. Bu\",\"doi\":\"10.23919/VLSIT.2019.8776493\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"In this paper, we present for the first time a “Gate-Cut-Last” integration scheme completed within the Replacement Metal Gate (RMG) module. This novel gate cut (CT) technique allows the scaling of gate extension length past the end fin which reduces parasitic capacitance, leakage and performance variation. In addition, we demonstrate that CT-in-RMG is a promising alternative integration process that can enable scaling for future logic technology nodes. Device, circuit and reliability results are shown to compare this novel CT-in-RMG process to the conventional gate cut method.\",\"PeriodicalId\":6752,\"journal\":{\"name\":\"2019 Symposium on VLSI Technology\",\"volume\":\"41 1\",\"pages\":\"T144-T145\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2019-06-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"1\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2019 Symposium on VLSI Technology\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.23919/VLSIT.2019.8776493\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2019 Symposium on VLSI Technology","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.23919/VLSIT.2019.8776493","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 1

摘要

在本文中,我们首次提出了在替换金属门(RMG)模块中完成的“门-切割-最后”集成方案。这种新颖的栅极切割(CT)技术允许栅极延伸长度超过端鳍的缩放,从而减少寄生电容,泄漏和性能变化。此外,我们还证明了CT-in-RMG是一种很有前途的替代集成过程,可以实现对未来逻辑技术节点的扩展。器件、电路和可靠性结果表明,这种新的CT-in-RMG工艺与传统的栅极切割方法进行了比较。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
Gate-Cut-Last in RMG to Enable Gate Extension Scaling and Parasitic Capacitance Reduction
In this paper, we present for the first time a “Gate-Cut-Last” integration scheme completed within the Replacement Metal Gate (RMG) module. This novel gate cut (CT) technique allows the scaling of gate extension length past the end fin which reduces parasitic capacitance, leakage and performance variation. In addition, we demonstrate that CT-in-RMG is a promising alternative integration process that can enable scaling for future logic technology nodes. Device, circuit and reliability results are shown to compare this novel CT-in-RMG process to the conventional gate cut method.
求助全文
通过发布文献求助,成功后即可免费获取论文全文。 去求助
来源期刊
自引率
0.00%
发文量
0
×
引用
GB/T 7714-2015
复制
MLA
复制
APA
复制
导出至
BibTeX EndNote RefMan NoteFirst NoteExpress
×
提示
您的信息不完整,为了账户安全,请先补充。
现在去补充
×
提示
您因"违规操作"
具体请查看互助需知
我知道了
×
提示
确定
请完成安全验证×
copy
已复制链接
快去分享给好友吧!
我知道了
右上角分享
点击右上角分享
0
联系我们:info@booksci.cn Book学术提供免费学术资源搜索服务,方便国内外学者检索中英文文献。致力于提供最便捷和优质的服务体验。 Copyright © 2023 布克学术 All rights reserved.
京ICP备2023020795号-1
ghs 京公网安备 11010802042870号
Book学术文献互助
Book学术文献互助群
群 号:481959085
Book学术官方微信