{"title":"基于环延迟线技术的全数字时域模数转换器设计","authors":"Hua Fan, Tong Xu, Jianming Liu, Q. Feng","doi":"10.1109/ICICDT51558.2021.9626479","DOIUrl":null,"url":null,"abstract":"A novel voltage-to-time converter (VTC) with high linearity and wide dynamic input range is used for low-power time-domain ADC in this paper, which combines the advantages of body bias technique and current mirror technique. The proposed time-domain ADC (T-ADC) consists of ring delay line, counter, encoder and subtractor. The time-domain ADC is implemented based on the XFAB 0.18μm COMS standard process, and the overall power consumption is 37.7μW under a 1.8V supply voltage. The simulated ENOB, SNDR, and SFDR are 10.72-bits, 66.31dB, and 76.13dB respectively at the Nyquist frequency.","PeriodicalId":6737,"journal":{"name":"2021 International Conference on IC Design and Technology (ICICDT)","volume":"35 1","pages":"1-4"},"PeriodicalIF":0.0000,"publicationDate":"2021-09-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"Design of an All-digital Time Domain Analog-to-digital Converter Based on Ring Delay Line Technology\",\"authors\":\"Hua Fan, Tong Xu, Jianming Liu, Q. Feng\",\"doi\":\"10.1109/ICICDT51558.2021.9626479\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A novel voltage-to-time converter (VTC) with high linearity and wide dynamic input range is used for low-power time-domain ADC in this paper, which combines the advantages of body bias technique and current mirror technique. The proposed time-domain ADC (T-ADC) consists of ring delay line, counter, encoder and subtractor. The time-domain ADC is implemented based on the XFAB 0.18μm COMS standard process, and the overall power consumption is 37.7μW under a 1.8V supply voltage. The simulated ENOB, SNDR, and SFDR are 10.72-bits, 66.31dB, and 76.13dB respectively at the Nyquist frequency.\",\"PeriodicalId\":6737,\"journal\":{\"name\":\"2021 International Conference on IC Design and Technology (ICICDT)\",\"volume\":\"35 1\",\"pages\":\"1-4\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2021-09-15\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2021 International Conference on IC Design and Technology (ICICDT)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ICICDT51558.2021.9626479\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2021 International Conference on IC Design and Technology (ICICDT)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICICDT51558.2021.9626479","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Design of an All-digital Time Domain Analog-to-digital Converter Based on Ring Delay Line Technology
A novel voltage-to-time converter (VTC) with high linearity and wide dynamic input range is used for low-power time-domain ADC in this paper, which combines the advantages of body bias technique and current mirror technique. The proposed time-domain ADC (T-ADC) consists of ring delay line, counter, encoder and subtractor. The time-domain ADC is implemented based on the XFAB 0.18μm COMS standard process, and the overall power consumption is 37.7μW under a 1.8V supply voltage. The simulated ENOB, SNDR, and SFDR are 10.72-bits, 66.31dB, and 76.13dB respectively at the Nyquist frequency.
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