机器学习在FPGA布局中的拥塞管理和可达性预测

Hannah Szentimrey, Abeer Y. Al-Hyari, Jérémy Foxcroft, T. Martin, D. Noel, G. Grewal, S. Areibi
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引用次数: 8

摘要

现场可编程门阵列(fpga)的放置是实现设计闭合的最重要但耗时的步骤之一。本文提出将三个独特的机器学习模型集成到最先进的分析放置工具GPlace3.0中,目的是显着减少放置运行时间。第一个模型MLCong基于线性回归,取代了GPlace3.0中目前用于估计交换机级拥塞的计算成本高昂的全局路由器。第二个模型DLManage是一个卷积编码器-解码器,它使用基于MLCong生成的交换机级拥塞估计的热图来动态确定应用于每个交换机的膨胀量,以解决拥塞。第三个模型DLRoute是一个卷积神经网络,它使用之前的热图来预测放置解决方案是否可路由。一旦确定放置解决方案是可路由的,就可以避免进一步的优化,从而改善运行时间。使用Xilinx Inc.提供的372个基准测试获得的实验结果表明,当将所有三种模型集成到GPlace3.0中时,放置运行时间平均减少48%。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
Machine Learning for Congestion Management and Routability Prediction within FPGA Placement
Placement for Field Programmable Gate Arrays (FPGAs) is one of the most important but time-consuming steps for achieving design closure. This article proposes the integration of three unique machine learning models into the state-of-the-art analytic placement tool GPlace3.0 with the aim of significantly reducing placement runtimes. The first model, MLCong, is based on linear regression and replaces the computationally expensive global router currently used in GPlace3.0 to estimate switch-level congestion. The second model, DLManage, is a convolutional encoder-decoder that uses heat maps based on the switch-level congestion estimates produced by MLCong to dynamically determine the amount of inflation to apply to each switch to resolve congestion. The third model, DLRoute, is a convolutional neural network that uses the previous heat maps to predict whether or not a placement solution is routable. Once a placement solution is determined to be routable, further optimization may be avoided, leading to improved runtimes. Experimental results obtained using 372 benchmarks provided by Xilinx Inc. show that when all three models are integrated into GPlace3.0, placement runtimes decrease by an average of 48%.
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