分层前端物理设计解决方案驱动改进的移交

W. Dai, M. Courtoy
{"title":"分层前端物理设计解决方案驱动改进的移交","authors":"W. Dai, M. Courtoy","doi":"10.1109/ISQED.2002.996799","DOIUrl":null,"url":null,"abstract":"A design methodology for the implementation of multimillion gate system-on-chip designs is described The new methodology is based on the creation of a physical prototype early in the back-end design process. The prototype is generated in a fraction of the time required to complete the traditional back-end flow but still maintains very high correlation with the final design. The physical prototype becomes the 'hub' where many design implementation decisions can be optimized by leveraging the short iteration times. Hierarchical design methodologies benefit from the prototyping stage by enabling a more optimal partitioning. The physical prototype also alters the nature of the hand-off model between front-end and back-end designers. The netlist can now be quickly validated using the prototype: the physical reality is being injected early in the design process resulting in fewer iterations between front-end and back-end.","PeriodicalId":20510,"journal":{"name":"Proceedings International Symposium on Quality Electronic Design","volume":null,"pages":null},"PeriodicalIF":0.0000,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"Hierarchical front-end physical design solution drives modified hand-off\",\"authors\":\"W. Dai, M. Courtoy\",\"doi\":\"10.1109/ISQED.2002.996799\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A design methodology for the implementation of multimillion gate system-on-chip designs is described The new methodology is based on the creation of a physical prototype early in the back-end design process. The prototype is generated in a fraction of the time required to complete the traditional back-end flow but still maintains very high correlation with the final design. The physical prototype becomes the 'hub' where many design implementation decisions can be optimized by leveraging the short iteration times. Hierarchical design methodologies benefit from the prototyping stage by enabling a more optimal partitioning. The physical prototype also alters the nature of the hand-off model between front-end and back-end designers. The netlist can now be quickly validated using the prototype: the physical reality is being injected early in the design process resulting in fewer iterations between front-end and back-end.\",\"PeriodicalId\":20510,\"journal\":{\"name\":\"Proceedings International Symposium on Quality Electronic Design\",\"volume\":null,\"pages\":null},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2002-08-07\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Proceedings International Symposium on Quality Electronic Design\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ISQED.2002.996799\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings International Symposium on Quality Electronic Design","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ISQED.2002.996799","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 0

摘要

描述了一种用于实现百万门系统芯片设计的设计方法。这种新方法是基于在后端设计过程的早期创建物理原型。原型的生成只需要完成传统后端流程所需的一小部分时间,但仍然与最终设计保持非常高的相关性。物理原型成为“枢纽”,许多设计实现决策可以通过利用较短的迭代时间来优化。分层设计方法通过实现更优的划分而受益于原型阶段。物理原型还改变了前端和后端设计人员之间的交接模型的性质。现在可以使用原型快速验证网表:在设计过程的早期注入物理现实,从而减少前端和后端之间的迭代。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
Hierarchical front-end physical design solution drives modified hand-off
A design methodology for the implementation of multimillion gate system-on-chip designs is described The new methodology is based on the creation of a physical prototype early in the back-end design process. The prototype is generated in a fraction of the time required to complete the traditional back-end flow but still maintains very high correlation with the final design. The physical prototype becomes the 'hub' where many design implementation decisions can be optimized by leveraging the short iteration times. Hierarchical design methodologies benefit from the prototyping stage by enabling a more optimal partitioning. The physical prototype also alters the nature of the hand-off model between front-end and back-end designers. The netlist can now be quickly validated using the prototype: the physical reality is being injected early in the design process resulting in fewer iterations between front-end and back-end.
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